Taiwan Semiconductor Manufacturing Comp. Ltd.

YingKit Felix Tsui

Wei-Kang Liu

Chih-Tsung Shih

Hau-Yan Lu

Wen-Shun Lo

Tai-Yi Wu

Hsin-Li Cheng

Yu-Chi Chang

Shu-Hui Su

Hsin-li Cheng

Lee-Shian Jeng

Feng Yuan

Min-Hsiang Hsu

Shih-Hsien Chen

Sui-Ying Hsu

Jyun-Ying Lin

Cheng-Tse Tang

Ting-Chen Hsu

Jing-Hwang Yang

Shi-Min Wu

Cheng-tse Tang

Shih-fen Huang

Jing-hwang Yang

Liang-tai Kuo

Shu-hui Su

A method includes receiving a silicon substrate; forming a first doped region and a second doped region in the silicon substrate; forming a third doped region and fourth doped region on upper portions of the first doped region and the second doped region, respectively; and patterning the silicon substrate to form an optical modulator. The optical modulator includes: a first section; a second section and a third section at least formed from the first and second doped regions, respectively; a fourth section, including a first height less than that of the first section and the second section and arranged between the first section and the second section, the fourth section being an undoped region; and a fifth section immediately adjacent to the fourth section, the fifth section including a height less than that of the first section and the second section and different from the first height.

Optical modulator and method of forming the same

A method of forming a grating coupler includes: providing an initial design layout of the grating coupler, wherein the initial design layout includes: a taper section, comprising a pair of tapers; and a grating section coupled to the taper section, the grating section having an array of gratings, wherein the gratings includes gradually changing shapes, from a top-view perspective, from a first non-convex octagonal shape of a central grating, at a center of the grating section, of one of a second non-convex octagonal shape, a convex octagonal shape, and a quadrilateral shape, to an edge grating near an edge of the grating section. The method further includes: converting the initial design layout into a revised design layout through an optical proximity correction operation; and manufacturing the grating coupler using the revised design layout.

Two-dimensional grating coupler and method of forming the same

A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.

Memory device

A method for manufacturing an integrated circuit device is provided. The method includes: providing a photonic structure including an insulating structure and an optical coupler embedded in the insulating structure; and removing a portion of the insulating structure to expose a coupling surface of the optical coupler and form a light reflective structure corresponding to the coupling surface.

Method for manufacturing silicon photonic device and silicon photonic device thereof

Various embodiments of the present disclosure are directed towards an integrated circuit. The integrated circuit includes a substrate having an upper face and a lower face. The upper face includes a central region and an outer sidewall that laterally surrounds the central region and that extends from the upper face to the lower face. An optical edge coupler is disposed over the upper face of the substrate and extends in a first direction from the central region toward the outer sidewall. An outer sidewall of the optical edge coupler corresponds to the outer sidewall of the substrate and has a concave surface or a convex surface.

Facet profile to improve edge coupler beam pointing and coupling efficiency for photonics

A semiconductor structure includes a semiconductor substrate, a serpentine-shaped resistor, and a MOS transistor. The semiconductor substrate includes an isolation structure and an active region. The serpentine-shaped resistor is over the isolation structure. The serpentine-shaped resistor extends in a length direction and has a width that is equal to or greater than about 3.6 μm in a width direction. The MOS transistor is over the active region of the semiconductor substrate.

Semiconductor structure and method of manufacturing semiconductor structure

A semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.

Semiconductor die package and methods of formation

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a first dielectric layer, a second dielectric layer, a light modulator, a heater, and a first conductive contact. The first dielectric layer is disposed on the semiconductor substrate. The second dielectric layer is disposed on the first dielectric layer. The light modulator is disposed in the first dielectric layer. The heater is disposed in the second dielectric layer and above the light modulator. The first conductive contact is electrically connected to the light modulator. A top surface of the heater is coplanar with a top surface of the first conductive contact.

Semiconductor device and method for manufacturing the same

A method of fabricating an optical device comprises steps of forming a silicon-based optical component in a substrate; depositing an ILD layer on the substrate and the silicon-based optical component; forming a thermal tuning assembly comprising a first metallic material in the ILD layer and above the silicon-based optical component, wherein the thermal tuning assembly comprises a core above the silicon-based optical component, a plurality of grids spaced apart from the core, and a pair of neck portions connecting the grids to the core, wherein a width of a strip in each grid is greater than a width of the core; forming at least one conductive plug comprising the first metallic material penetrating the ILD layer and coupled to the silicon-based optical component; and forming a plurality of conductive lines comprising a second metallic material coupled to the thermal tuning assembly.

Silicon-based optical device and method of fabricating the same

A semiconductor structure includes a waveguide and an optical attenuator. The waveguide is disposed over an insulating layer and configured to guide light. The optical attenuator is connected to the waveguide. The optical attenuator has a first surface and a second surface opposite the first surface, and a cross-sectional width of the optical attenuator decreases from the first surface to the second surface.

Semiconductor structure and method for forming the same

Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

Trench capacitor film scheme to reduce substrate warpage

An edge coupler, a waveguide structure and a method for forming a waveguide structure are provided. The edge coupler includes a substrate, a first cladding layer, a core layer and a first anti-reflection coating layer. The first cladding layer has a second sidewall aligned with a first sidewall of the substrate. The core layer has a third sidewall aligned with the second sidewall. The anti-reflection coating layer lines the first sidewall, the second sidewall and the third sidewall. A thickness of the anti-reflection coating layer varies along the first sidewall, the second sidewall and the third sidewall.

Edge coupler and waveguide structure and forming method thereof

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.

Method to improve data retention of non-volatile memory in logic processes

In some embodiments, the present disclosure relates to a device having a first waveguide and a second waveguide arranged over a substrate. The first waveguide has a first input terminal and a first output terminal, wherein the first input terminal is configured to receive light. The second waveguide is arranged laterally beside the first waveguide and has a second input terminal and a second output terminal. The second input terminal of the second waveguide is configured to receive light. The first waveguide further includes a first portion that has a different structure than surrounding portions of the first waveguide. The second waveguide further includes a second portion that has a different structure than surrounding portions of the second waveguide. The first waveguide is spaced apart at a maximum distance from the second waveguide at the first portion and the second portion.

Frequency- and process-insensitive splitting use multiple splitters in series

A semiconductor structure includes a substrate, a grating coupler structure over the substrate, a multi-layers film structure over the grating coupler structure. The multi-layers film structure include a first layer including a first refractive index, a second layer over the first layer and including a second refractive index and a third layer over the second layer and including a third refractive index. The second refractive index is greater than the first refractive index and is greater than the third refractive index of the third layer, and a thickness of each layer of the multi-layers film structure is within a range from λ/4 to λ2, λ is a wavelength of light.

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Cupertino, CA, United States of America

YingKit Felix Tsui