Cadence Design Systems, Inc.

Yinghong Zhou

Joel Reuben Phillips

Ilya Yusim

The time to test integrated circuits is increasing as a function of the complexity of integrated circuits and processes used to fabricate the integrated circuits. Embodiments of this disclosure include systems and methods for reducing the time to integrated circuits by reducing the number of devices individually modeled. Embodiments can reduce the number of modeled devices by combining two or more devices into a single combined device that models all discrete devices, but in a reduced form.

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San Jose, CA, United States of America

Yinghong Zhou