Sandisk Technologies Inc.

Sandisk Corporation

Micron Technology Incorporated

Western Digital Technologies, Inc.

Yingda Dong

Man Lung Mui

Liang Pang

Ching-Huang Lu

Hong-Yan Chen

Chris Avila

Jiahui Yuan

Jeffrey W Lutze

Gautam Ashok Dusija

Zhengyi Zhang

Masaaki Higashitani

Ken Oowada

Wei Zhao

Deepak Raghu

Gerrit Jan Hemink

Jayavel Pachamuthu

Seungpil Lee

Jian Feng Chen

Johann Alsmeier

Cynthia Hsu

Pao-Ling Koh

Xuehong Yu

Yanli Zhang

Dana Lee

Ashish Kumar Baraskar

Charles S Kwong

Chris Nga Yee Avila

Vinh Diep

Alexander Kwok-Tung Mak

Vinh Q Diep

Deepanshu Dutta

Hao Nguyen

Tien-Chien Kuo

Changyuan Chen

Yangyin Chen

Toru Ishigaki

James K Kai

Peter Rabkin

George Matamis

Henry Chin

Shih-Chung Lee

Alex Mak

Yukihiro Sakotsubo

Raghuveer S Makala

Nima Mokhlesi

Jun Xu

Xiying Costa

Hua-Ling Cynthia Hsu

Khanh Vinh Nguyen

Yongke Sun

Hitoshi Miwa

Yan Li

Chang Hua Siau

Yupin K Fong

Steven Theodore Sprouse

Henry Chien

Mohan Dunga

Teruhiko Kamei

Toru Miwa

Kwang-Ho Kim

Albert Fayrushin

Zhenyu Lu

Fumitoshi Ito

Fanglin Zhang

Akira Matsudaira

Manabu Sakai

Yosuke Kato

Haitao Liu

Sampath K Ratnam

Violante Moschiano

Hiroyuki Ogawa

Nian Niles Yang

Christopher John Petti

Kamal M Karda

Rahul Sharangpani

Shinji Sato

Fei Zhou

Jun Wan

Koichi Nishimura

Anubhav Khandelwal

Shuji Tanaka

Peng Zhang

Mrinal Kochar

Sateesh Koka

Masashi Yoshida

Daxin Mao

Kensuke Yamaguchi

Lee M Gavens

Somesh Peri

Nan Lu

Hiro Kinoshita

Yichao Huang

Yifen Liu

Matthias Baenninger

Han-Ping Chen

Yen-Lung Li

Wenguang Shi

Jeffrey Ming-Hung Tsai

Lei Lin

Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.

Multi-stage erase operation of memory cells in a memory sub-system

A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Fast program recovery with reduced programing disturbance in a memory device

A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.

Corrective program verify operation with improved read window budget retention

Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

Enhanced gradient seeding scheme during a program operation in a memory sub-system

A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.

Selective increase and decrease to pass voltages for programming a memory device

Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

Bias voltage schemes during pre-programming and programming phases

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

Memory device having memory cell strings and separate read and write control gates

Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Detrapping electrons to prevent quick charge loss during program verify operations in a memory device

An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods

A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

Distributed compaction of logical states to reduce program time

Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.

Short program verify recovery with reduced programming disturbance in a memory sub-system

A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.

Apparatus and methods for seeding operations concurrently with data line set operations

A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

Dual verify for quick charge loss reduction in memory cells

Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

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San Jose, CA, United States of America

Yingda Dong