Mediatek Corporation

Novatek Microelectronics Corp.

Ying-Zu Lin

Chao-Hsin Lu

Chih-Hou Tsai

Chin-Yu Lin

Chihhou Tsai

Rong-Sing Chu

Chia-Wei Su

Ji-Ting Chen

Shun-Hsun Yang

Li-Tang Lin

Wei-Hsiang Hung

Shan-Chih Tsou

Wei-Hao Tsai

Chia-Hsun Kuo

Chao Hsin Lu

A time-interleaved noise-shaping successive-approximation analog-to-digital converter (TI NS-SAR ADC) is shown. A first successive-approximation channel has a first set of successive-approximation registers, and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. A second successive-approximation channel has a second set of successive-approximation registers, and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. A fine comparator is provided to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. A noise-shaping circuit is provided to sample residues of the first and second successive-approximation channels for the fine comparator to finely adjust the first and second sets of successive-approximation registers.

Time-interleaved noise-shaping successive-approximation analog-to-digital converter

A noise-shaping successive approximation analog-to-digital converter (NS-SAR ADC) using a passive noise-shaping technique with 1-input-pair SAR comparator is introduced. A residue sampling and integration circuit is coupled between a DAC and the comparator, for sampling a residue voltage generated by the DAC and charge-sharing of the sampled residue voltage. A first integral capacitor is coupled between a first input terminal of a comparator and a first output terminal of a DAC. After a first residue capacitor samples a residue generated by the DAC, the first residue capacitor is coupled to the first integral capacitor for charge-sharing of the residue voltage.

Analog-to-digital converter

A charge compensation circuit for use in an analog-to-digital converter (ADC) includes at least one capacitor and at least one logic circuit. A first terminal of the capacitor is coupled to a reference voltage of the analog-to-digital converter. The logic circuit is configured to adjust a voltage at a second terminal of the capacitor according to a control signal. The control signal is determined according to at least one output bit from the analog-to-digital converter.

Charge compensation circuit and analog-to-digital converter with the same

A metal-oxide-metal (MOM) capacitor is provided in the present invention. The MOM capacitor includes a capacitor element, wherein the capacitor element includes a first electrode and a second electrode. A projection of the first electrode includes a closed pattern in the vertical projection direction. A projection of the second electrode is surrounded by the closed pattern of the projection of the first electrode in the vertical projection direction.

Metal-oxide-metal capacitor

A reference voltage generator for an analog-to-digital converter (ADC) includes a current source coupled to a power supply, and a first transistor coupled between the current source and a first resistive circuit. The first resistive circuit is coupled to the first transistor. The reference voltage generator further includes a second transistor having a gate coupled to the current source and a gate of the first transistor, for providing a reference voltage to the ADC, an impedance circuit coupled to the second transistor, for selectively providing a variable impedance.

Reference voltage generator and analog-to-digital converter

An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.

Input buffer and analog-to-digital converter

A display driver, which comprises: a first predetermined voltage level providing apparatus, for providing a first predetermined voltage level group comprising at least one first predetermined voltage level; a first image data providing apparatus, for outputting a first image data; and a detection controlling circuit, for determining if an output terminal of the first image data providing apparatus is pre-charged to the first predetermined voltage level according to a relation between an absolute value of a voltage level of the first image data and an absolute value of the first predetermined voltage level.

Display driver and display diving method

An interface circuit for signal transmission includes an amplifying circuit, a de-skew circuit and a latching unit. The amplifying circuit receives an input clock signal and outputs an output clock signal after amplifying the input clock signal. The de-skew circuit receives the output clock signal and outputs a de-skew clock signal as a trigger signal after removing a skew time of the output clock signal. The latching unit includes multiple sampling circuits, respectively receives multiple inputting data signals. The sampling circuits are controlled by the trigger signal to sample the inputting data signals and output multiple outputting data signals. The voltage amplitudes of the outputting data signals are larger than the voltage amplitudes of the inputting data signals and satisfy a required voltage amplitude by a subsequent circuit.

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Taichung, Taiwan

Ying-Zu Lin