Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying Zhang

Ziwei Fang

Jeffrey Junhao Xu

Shu-Huei Suen

Tien-Chih Cheng

Jeff J Xu

Chien-An Chen

Yu-Cheng Liu

Ying Xiao

Shih-Hung Chen

Jian-Huah Chiou

Chen-Chiao Kao

An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm. In an embodiment, the pocket has a depth of between about 1 nanometer to about 30 nanometers.

Tunneling field effect transistor (TFET) with ultra shallow pockets formed by asymmetric ion implantation and method of making same

A wafer support device is provided. The wafer support device includes a plurality of support portions; and a bottom area located among the support portions, wherein the bottom area has a protective layer formed thereon. A method for processing a working surface of a wafer support device is also provided.

Wafer support device

An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.

Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same

An etching method comprises etching an oxide layer with a first dc bias of a plasma chamber, removing a photoresist layer with a second dc bias of the plasma chamber and etching through a liner film with a third dc bias of the plasma chamber. In order to reduce the copper deposition on the wall of the plasma chamber, the third dc bias is set to be less than the first and second dc bias.

Etching method and apparatus

An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.

Self-aligned source and drain structures and method of manufacturing same

A method includes forming a gate stack to cover a middle portion of a semiconductor fin, and doping an exposed portion of the semiconductor fin with an n-type impurity to form an n-type doped region. At least a portion of the middle portion is protected by the gate stack from receiving the n-type impurity. The method further includes etching the n-type doped region using chlorine radicals to form a recess, and performing an epitaxy to re-grow a semiconductor region in the recess.

Methods for forming FinFETs with self-aligned source/drain

An embodiment method of controlling threshold voltages in a fin field effect transistor (FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.

FinFET/tri-gate channel doping for multiple threshold voltage tuning

A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.

Methods for forming FinFETs having multiple threshold voltages

A wafer transport pod for storing or transporting semiconductor wafers during semiconductor wafer processing includes a body having a top panel, a bottom panel, a back panel, two side panels and a front panel. The two side panels are configured for receiving the semiconductor wafers therebetween. The two side panels have a plurality of separately hermetically sealed partitions inside the body, any two of the sealed partitions for sealing a wafer therebetween and for preventing wafer contamination. The front panel provides ingress and egress for the semiconductor wafers to and from the wafer transport pod.

Growing community of inventors

Hsin-Chu, Taiwan

Ying Zhang