Realtek Semiconductor Inc.

Ying-Yen Chen

Jih-Nung Lee

Chun-Yi Kuo

Po-Lin Chen

Wen-Hsuan Hsu

Jeong-Fa Sheu

Chao-Wen Tzeng

Yu-Cheng Lo

Chia-Jui Yang

Chia-Tso Chao

Pei-Ying Hsueh

Shuo-Fen Kuo

Li-Wei Deng

Hsiao Tzu Liu

Tzung-Jin Wu

Ching-Feng Su

Yin-Ping Chern

Chun-Yu Yang

Chih-Tung Chen

Tse-Wei Wu

Chun-yi Kuo

Shiou Wen Wang

Yu Yen Yang

Cheng-Yan Wen

Yu-Ting Li

Ming-Chung Wu

The present disclosure provides a clock control circuit and method for a circuitry. The circuitry includes a scan flip-flop circuit, an at-speed domain and a timing exception domain. The scan flip-flop circuit is configured to output data to the at-speed domain and the timing exception domain. The clock control circuit includes a first gate control circuit, a first gate circuit, a second gate control circuit and a second gate circuit. The first gate circuit is controlled by a first control signal output by the first gate control circuit, a scan enable signal and a scan mode signal to block or output a clock signal to the scan flip-flop circuit. The second gate circuit is controlled by a second control signal output by the second gate control circuit to block or output an output signal of the scan flip-flop circuit to the timing exception domain.

Clock control circuit and method

A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.

Test circuit and method for reading data from a memory device during memory dump

A scan chain designing method includes: obtaining test points according to a gate-level netlist; determining integers M and N, wherein M and N are no greater than an amount X of the test points; selecting M and N test points to be a first and second set test points according to a priority; obtaining a first test coverage and a first test pattern count according to the first set test points and obtaining a second test coverage and a second test pattern count according to the second set test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimum amount O according to the predicted test coverage curve, the first and second test pattern counts, wherein O is no greater than X; and selecting O test points to arrange a scan chain according to the priority and the optimum amount O.

Scan chain designing and circuit testing method

The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.

Calibration data generation circuit and associated method

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.

Device for detecting margin of circuit operating at certain speed

A reliability detection device includes a control circuit, oscillator circuits, and an output circuit. The control circuit is configured to generate enable signals according to a mode signal. The oscillator circuits output oscillating signals, in which each of the oscillator circuits is configured to generate a corresponding oscillating signal in the oscillating signals according to a switching signal when the mode signal has a first logic value, and generate the corresponding oscillating signal according to a corresponding enable signal in the enable signals when the mode signal has a second logic value, and the switching signal is associated with a functional circuit. The output circuit is configured to output a detection signal according to the oscillating signals when the mode signal has the second logic value, in which the detection signal is to indicate a reliability of the functional circuit.

Reliability detection device and reliability detection method

An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

Electronic device test database generating method and electronic device test database generating apparatus

A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.

Circuit having multiple scan modes for testing

The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Circuit testing system and circuit testing method

The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.

Disclosed is a measuring circuit for quantizing variations in the operating speed of a target circuit. The measuring circuit includes: a signal generator configured to generate a predetermined signal; an adjustable delay circuit configured to generate a first and second delay signals according to the predetermined signal respectively; a signal detector configured to detect the first and second delay signals respectively and thereby generate a first and second detection results respectively; and a calibrating circuit configured to enable a first and second numbers of delay units of the adjustable delay circuit according to the first and second detection results respectively so as to make each of the delays respectively caused by the first and second numbers of delay units be less than a delay threshold, in which the first and second numbers relate to the operating speed of the target circuit operating in the first and second conditions respectively.

Measuring circuit for quantizing variations in circuit operating speed

Disclosed is a circuit operating speed detecting circuit configured to detect an operating speed of a target circuit during a monitor mode. The circuit operating speed detecting circuit includes a signal generator, an adjustable delay circuit, and a signal detector. During the monitor mode, the signal generator generates a predetermined signal in a current operating condition, the adjustable delay circuit generates a delay signal according to the predetermined signal in the current operating condition, and the signal detector detects the degree of delay of the delay signal in the current operating condition so as to generate a first result if the degree of delay is not greater than a predetermined threshold and generate a second result if the degree of delay is greater than the predetermined threshold, in which the first and the second results are related to the operating speed of the target circuit.

Circuit operating speed detecting circuit

The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.

Test device for testing integrated circuit

The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N&#xd7;M records of quiescent DC current (IDDQ) data; generating N reference values according to the N&#xd7;M records, in which each of the N reference values is generated according to M record(s) of the N&#xd7;M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N&#xd7;M records by the reference order so as to obtain reordered N&#xd7;M records; generating an IDDQ range according to the reordered N&#xd7;M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.

Integrated circuit test method

An electronic device includes a controller, a user interface and a sensor. The user interface and the sensor are coupled to the controller. The user interface is configured to send a first user command to the controller to control the controller to enter a burst mode. The controller is configured to control the sensor to continuously sense a chip or an environment where the chip is located to generate multiple sensing values, and to generate a sensing data according to the sensing values after the controller receives the first user command to enter the burst mode.

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Hsinchu, Taiwan

Ying-Yen Chen