Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying Xiao

Chin-Hsiang Lin

Yen-Shuo Su

Shih-Hung Chen

Chien-An Chen

Chyi Shyuan Chern

Ying Zhang

Yu-Lung Yang

A control system for a plasma treatment apparatus includes a wafer treatment device. The wafer treatment device includes a vapor chamber and an upper electrode assembly. The upper electrode assembly includes a gas distribution plate having a plurality of holes. The upper electrode assembly includes an upper electrode having at least one gas nozzle and at least one controllable valve connected to the at least one gas nozzle for controlling a flow of gas from a gas supply to the holes via the at least one gas nozzle. The at least one gas nozzle is separated from the gate distribution plate by a gap. The control system includes a measurement device configured to measure a thickness profile of a wafer. The control system includes a controller configured to generate a control signal. The at least one controllable valve is configured to be adjusted based on the control signal.

Control system for plasma chamber having controllable valve

Control system for plasma chamber having controllable valve and method of using the same

The present disclosure relates to a semiconductor body etching apparatus having a multi-zone end point detection system. In some embodiments, the multi-zone end point detection system has a processing chamber that houses a workpiece that is etched according to an etching process. A plurality of end point detector (EPD) probes are located within the processing chamber. Respective EPD probes are located within different zones in the processing chamber, thereby enabling the detection of end point signals from multiple zones within the processing chamber. The detected end point signals are provided from the plurality of EPD probes to an advanced process control (APC) unit. The APC unit is configured to make a tuning knob adjustment to etching process parameters based upon the detected end point signals and to thereby account for etching non-uniformities.

Multi-zone EPD detectors

This description relates to a plasma treatment apparatus including a vapor chamber, a gas supply and an upper electrode assembly. The upper electrode assembly includes a gas distribution plate having a plurality of holes in a bottom surface thereof and an upper electrode having at least one gas nozzle and at least one controllable valve connected to the at least one gas nozzle. The plasma treatment apparatus further includes a controller configured to generate a control signal. The at least one controllable valve is configured to be adjusted based on the control signal. A control system and a method of controlling a controllable valve are also described.

Plasma chamber having an upper electrode having controllable valves and a method of using the same

In some embodiments, the present disclosure relates to a plasma etching system having direct and localized plasma sources in communication with a processing chamber. The direct plasma is operated to provide a direct plasma to the processing chamber for etching a semiconductor workpiece. The direct plasma has a high potential, formed by applying a large bias voltage to the workpiece. After etching is completed the bias voltage and direct plasma source are turned off. The localized plasma source is then operated to provide a low potential, localized plasma to a position within the processing chamber that is spatially separated from the workpiece. The spatial separation results in formation of a diffused plasma having a zero/low potential that is in contact with the workpiece. The zero/low potential of the diffused plasma allows for reactive ashing to be performed, while mitigating workpiece damage resulting from ion bombardment caused by positive plasma potentials.

Plasma etcher design with effective no-damage in-situ ash

The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface.

Source/drain structure of semiconductor device

A system and method of controlling a semiconductor wafer fabrication process. The method includes positioning a semiconductor wafer on a wafer support assembly in a wafer processing module. A signal is transmitted from a signal emitter positioned at a predetermined transmission angle relative to an axis normal to the wafer support assembly to check leveling of the wafer in the module, so that the signal is reflected from the wafer. The embodiment includes monitoring for the reflected signal at a predetermined reflectance angle relative to the axis normal to the wafer support assembly at a signal receiver. A warning indication is generated if the reflected signal is not received at the signal receiver.

Systems and methods of controlling semiconductor wafer fabrication processes

An etching method comprises etching an oxide layer with a first dc bias of a plasma chamber, removing a photoresist layer with a second dc bias of the plasma chamber and etching through a liner film with a third dc bias of the plasma chamber. In order to reduce the copper deposition on the wall of the plasma chamber, the third dc bias is set to be less than the first and second dc bias.

Etching method and apparatus

A wafer handling system with apparatus for transporting wafers between semiconductor fabrication tools. In one embodiment, the apparatus is a loadport bridge mechanism including an enclosure having first and second mounting ends, a docking port at each end configured and dimensioned to interface with a loadport of a semiconductor tool, and at least one wafer transport robot operable to transport a wafer between the docking ports. The wafer transport robot hands off or receives a wafer to/from a tool robot at the loadports of a first and second tool. The bridge mechanism allows one or more wafers to be transferred between loadports of different tools on an individual basis without reliance on the FAB's automated material handling system (AMHS) for bulk wafer transport inside a wafer carrier such as a FOUP or others.

Loadport bridge for semiconductor fabrication tools

A chuck and a wafer supported thereon are rotated during a plasma process or a film deposition process to reduce thickness non-uniformity of a film processed or deposited on the wafer.

Plasma process, film deposition method and system using rotary chuck

A method includes measuring a depth of a shallow trench isolation (STI) region below a surface of a substrate. The STI region is filled with an oxide material. The substrate has a nitride layer above the surface. A thickness of the nitride layer is measured. A first chemical vapor etch (CVE) of the oxide material is performed, to partially form a recess in the STI region. The first CVE removes an amount of the oxide material less than the thickness of the nitride layer. The nitride layer is removed by dry etching. A remaining height of the STI region is measured after removing the nitride. A second CVE of the oxide material in the STI region is performed, based on the measured depth and the remaining height, to form at least one fin having a desired fin height above the oxide in the STI region without an oxide fence.

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Zhubei, Taiwan

Ying Xiao