Inventec Corp.

Inventec (pudong) Technology Corporation

Ying-Xian Han

Jian-Xin Huang

Zhi-Feng Zhu

A server power saving system includes a motherboard and a backplane. The motherboard includes a CPLD, a basic I/O control chip electrically connected with the CPLD, and a clock chip electrically connected with the CPLD. The basic I/O control chip includes a basic I/O control program The backplane includes a HD microcontroller electrically connected with the CPLD and a HD connection port electrically connected with the HD microcontroller and the clock chip. The HD microcontroller sends clock enable signal to the CPLD when a HD is electrically connected with the HD connection port. The CPLD transmits clock enable signal to the basic I/O control chip. The basic I/O control chip sends confirmation signal to the CPLD according to clock enable signal, and the CPLD determines whether to drive the clock chip to send clock signal to the HD connection port according to a content of confirmation signal.

Server power saving system and server power saving method

A BIOS switching device adapted to a server comprises a switching module, a CPLD, a storage module and a BMC. The switching module comprises a movable switching element locating at a first position or at a second position and a plurality of hardware pins. The hardware pins are logical low when the switching element locates at the second position and remains unchanged logical level when the switching element locates at the first position. The CPLD electrically connects to the switching module, comprising a plurality of input signals respectively coupled to the plurality of hardware pins. The CPLD generates an output signal according to the plurality of input signals. The BMC activates a first BIOS or a second BIOS from the storage module according to the logical level of the output signal of the CPLD.

BIOS switching device

An electronic device having a temperature management function includes a platform controller hub (PCH), a complex programmable logic device (CPLD) and a hardware monitor. The PCH includes a first temperature sensor for sensing the first temperature of the PCH. The CPLD includes a memory and is coupled to the PCH. The CPLD reads the first temperature sensed by the first temperature sensor and saves it in the memory. The CPLD searches for an offset value in the memory and generates a device temperature according to the offset value and the first temperature. The hardware monitor is coupled to the CPLD and reads the device temperature.

Electronic device having temperature management function

A chip programming device comprises a chip socket and a protecting circuit. The chip socket is configured to accommodate a chip to be programmed, is electrically connected with a circuit board, and comprises a power terminal and a ground terminal which are configured to connect to the chip. The protecting circuit is disposed on the circuit board, and comprises a power input terminal, an enable signal input terminal and a power output terminal which is electrically connected to the power terminal of the chip socket. The protecting circuit receives a power signal via the power input terminal, receives an enable signal via the enable signal input terminal, provides the power signal to the chip socket via the power output terminal when the enable signal has a first electric potential, and terminates the power signal to the chip socket when the enable signal has a second electric potential.

Chip programming device and protecting method thereof

A computer has a platform controller hub (PCH), a field replaceable unit (FRU), a memory, a complex programmable logic device (CPLD) and a basic input output system (BIOS) chip. The PCH has a first port and a second port. The FRU and the memory are both electrically connected to the first port of the PCH. The CPLD is electrically connected to the second port of the PCH, and used for detecting an indicating signal from the second port to selectively generate a reset signal. The BIOS chip is electrically connected to the PCH, the FRU, and the CPLD, and used for making the computer rebooted in a manufacturer mode or a normal mode according to the reset signal.

Computer and controlling method thereof

In a system and a method for controlling temperatures of a computer, an infrared induction module and a temperature-detecting module are applied to obtain position information and temperature information of a device module, and the position information and the temperature information are further analyzed and judged by a baseboard management controller to carry out different control means for the device module under different operation status and temperature conditions. Through the system and the method, the device module can be kept in operating under an operation temperature less than a predetermined temperature, so as to ensure the normal operation of the device module and to further promote the efficiency of test, maintenance and repair.

System and method for controlling temperatures of computer

In the system, a buffer and a multiplexer are electrically connected to an IC interface and a control interface of a PCH. A plurality of memory are electrically connected to the buffer and corresponding to a first IC address respectively. A plurality of card slots are electrically connected to the multiplexer for connecting to a function card so that the function card is corresponding to a second IC address. When the first IC address is distinct to the second IC address, the PCH triggers the multiplexer to be enabled through the control interface to have the function card electrically connected to the PCH through the IC interface. When the first IC address is the same as the second IC address, the PCH triggers the multiplexer or the buffer to be disabled through the control interface to have the function card or the memories electrically connected to the PCH through the IC interface.

Prevented inter-integrated circuit address conflict service system and method thereof

A power failure monitoring system and a method are disclosed herein, where the power failure monitoring system includes a motherboard, a board, a complex programmable logic device (CPLD) and a baseboard management controller (BMC) module. The motherboard includes a central processing unit (CPU) power and a non-CPU power. The board includes a board power. The BMC module includes a register that is electrically coupled to the CPLD. The CPLD is configured to execute a shutdown process when power failure occurs, identify a power failure type, and determine whether to execute a restart process according to the power failure type. If the restart process is executed and a count of the restart process reaches a predetermined count, the CPLD records lock information in the register. The BMC module is configured to record the count of the restart process, and execute a lock process according to the lock information.

Power failure detection system and method

A power source protection device and a power source protection method are disclosed herein. The power source protection device includes a power supply, a power source managing unit and a signal sending unit. The power supply provides a DC input voltage. The power source managing unit receives the DC input voltage, and when a determining voltage related to the input voltage is larger than a set voltage, enters a startup state and outputs a supply voltage. After receiving the supply voltage, the power source managing unit transforms the DC input voltage into a standby power output voltage and provides the standby power output voltage when the signal sending unit sends a control signal to the power source managing unit within an enabling time. VVhen it has not received the control signal within the enabling time, the power source managing unit enters a shutdown state.

Power source protection device and method

In the updating system, the CPLD has an original firmware version data and a PCH of a processing chip includes a storage which stores an updating identification code table and at least one updating firmware data. The updating identification code table has at least one updating identification code which is corresponded to the updating firmware data respectively. A processing unit of the processing chip has an identification code and an updating program. In the updating method, a first step is provided to capture the updating identification code table after the updating program is triggered. A second step is provided to capture the updating firmware data when the identification code is same as the updating identification code. A third step is provided to replace the original firmware version data from the updating firmware data through the PCH.

Updating system of firmware of complex programmable logic device and updating method thereof

A HDD backboard includes a power detecting circuit and a first working circuit. The power detecting circuit is configured to determine whether a plurality of voltage rails of the HDD backboard are normal, so as to output a power detecting signal. The first working circuit is coupled with the power detecting circuit and configured to receive the power detecting signal and output an HDD backboard determining signal. The motherboard includes a second working circuit and a CPLD. The CPLD is configured to receive the HDD backboard determining signal The CPLD is configured to determine whether the HDD backboard is absent when the electronic device operates in a standby mode and determine whether the voltage rails are failed when the electronic device operates in a working mode.

Electronic device

An electronic apparatus includes a casing, a first sliding tray module, a second sliding tray module, a switch module and a main board. The first sliding tray module includes a first belt unit, a baffle is disposed on one end of the first belt unit. The switch module includes an elastic piece and a switch. The first sliding tray module and/or the second sliding tray module slide/slides in or out to make the elastic piece and the baffle touched or untouched. The switch generates a switch signal according to whether the elastic piece and the baffle being touched or untouched. While the elastic piece and the baffle are untouched, the main board is configured to generate a detecting time according to the switch signal, and while the detecting time is longer than a safe time, the main board generates a warning signal through the electronic apparatus.

Electronic disk drive apparatus

A server includes a control module, a power-supply unit, a storage unit and a switch unit. The control module is electrically connected to a storage device. When the server is powered on, a first power is transmitted to from the power-supply unit to the storage unit and the switch unit, and received by the switch unit to generate a third power. When the server is powered off, the storage unit is triggered to transmit a second power to the switch to make the switch transmit the third power. The control module is provided to control a transmission information between the storage device and a buffer of the control module. When the server is powered on again, the control module continually works according to the transmission information stored in the buffer.

Server storing data and control information for repowering operation

A computing system and method for respectively displaying information corresponding to host computer under booting state or standby state is disclosed in the present invention. In the method, the computing system is provided to determine whether the host computer is under a booting state or a standby state. When the host computer is under the booting state, a display module of the computing system displays the control information of the baseboard management controller. When the host computer is under the standby state, the display module displays the information about BIOS Power-on self-test (POST).

Growing community of inventors

Shanghai, China

Ying-Xian Han