Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying-Wei Li

Chii-Horng Li

Chien-Chang Su

Chien-I Kuo

Yen-Ru Lee

Li-Li Su

Heng-Wen Ting

Jung-Chi Tai

Che-Hui Lee

Lilly Su

Yi-Kai Tseng

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

FETs and methods of forming FETs

FETS and methods of forming FETS

A semiconductor device includes a semiconductor substrate, at least one first isolation structure, at least one second isolation structure, a source structure, a drain structure and a plurality of semiconductor fins. The first isolation structure and the second isolation structure are located on the semiconductor substrate. The source structure is located on the semiconductor substrate and the first isolation structure, in which at least one first gap is located between the source structure and the first isolation structure. The drain structure is located on the semiconductor substrate and the second isolation structure, in which at least one second gap is located between the drain structure and the second isolation structure. The semiconductor fins protrude from the semiconductor substrate, in which the semiconductor fins are spaced apart from each other, and connect the source structure and the drain structure.

FinFET device and method for fabricating the same

FETS and methods of forming FETs

A semiconductor device having n-type field-effect-transistor (NFET) structure and a method of fabricating the same are provided. The NFET structure of the semiconductor device includes a silicon substrate, at least one source/drain portion and a cap layer. The source/drain portion can be disposed within the silicon substrate, and the source/drain portion comprises at least one n-type dopant-containing portion. The cap layer overlies and covers the source/drain portion, and the cap layer includes silicon carbide (SiC) or silicon germanium (SiGe) with relatively low germanium concentration, thereby preventing n-type dopants in the at least one n-type dopant-containing portion of the source/drain portion from being degraded after sequent thermal and cleaning processes.

Semiconductor device having NFET structure and method of fabricating the same

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Taichung, Taiwan

Ying-Wei Li