Mips Technologies, Inc.

Arm Finance Overseas Limited

Ying-wai Ho

John L Kelley

Radhika Thekkath

G Michael Uhler

Chandlee B Harrell

XingYu Jiang

Xing Yu Jiang

Michael J Schulte

Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.

Processor with improved accuracy for multiply-add operations

A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.

Processor having a compare extension of an instruction set architecture

Floating-point units (FPUs) and processors having a 'flush-to-nearest' operating mode that provides improved accuracy over a conventional 'flush-to-zero' mode. The FPU or processor includes an operand processing section and an operand flush section. For each floating-point operation, the operand processing section receives and processes one or more input operands to provide a preliminary result. The operand flush section determines whether the preliminary result falls within one of a number of ranges of values and sets the preliminary result to one of a number of set values if the preliminary result falls within one of the ranges. In a specific implementation, a first range of values is defined to include values greater than zero and less than half of a minimum normalized number (i.e., 0&#x3c;|y|&#x3c;+a/2), a second range of values is defined to include values equal to or greater than +a/2 and less than +an, (i.e., a/2&#x2266;|y|&#x3c;a), and the preliminary result is set to zero if it falls within the first range and to +aor &#x2212;a(depending on the sign bit) if it falls within the second range.

Floating-point processor with operating mode having improved accuracy and high performance

The accuracy of approximating the reciprocal and the reciprocal square root of a number (N) is improved. Approximating the reciprocal of N includes: (a) estimating the reciprocal of N to produce an estimate (X); (b) determining a first intermediate result (IR1) according to the equation: IR1=1&#x2212;N*X; (c) multiplying IR1 by Xto produce a second intermediate result (IR2); and (d) adding Xto IR2 to produce an approximation of the reciprocal of N. Approximating the reciprocal square root includes: (a) estimating the reciprocal square root of N to produce X; (b) multiplying Xby N to produce IR1; (c) determining IR2 according to the equation: IR2=(1&#x2212;X*IR1)/2; (d) multiplying IR2 by Xto produce a third intermediate result (IR3); and (e) adding IR3 to Xto produce an approximation of the reciprocal square root of the number.

System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit

A processor having a conditional branch extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to branching if, for example, either one of two condition codes is false or true, if any of three condition codes are false or true, or if any one of four condition codes are false or true.

Processor having a conditional branch extension of an instruction set architecture

A processor having an arithmetic extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to reduction add, reduction multiply, reciprocal, and reciprocal square root.

Processor having an arithmetic extension of an instruction set architecture

Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. The intermediate result from the multiplier unit is processed (i.e., rounded) into representations that are more easily managed in the adder unit. However, some of the processing (i.e., normalization and exponent adjustment) to generate an IEEE-compliant representation is deferred to the adder unit. By combining and deferring some of the processing steps for the intermediate result, circuit complexity is reduced and operational performance is improved.

Floating-point processor with improved intermediate result handling

A method and apparatus predict whether an overflow or underflow floating-point exception could occur as a result of a data processing system performing a particular floating-point operation. Predictions are made based on at least one overflow threshold value, at least first and second underflow threshold values, and a preliminary result exponent value derived from the values of the exponents of the floating-point numbers that are about to be acted upon. The preliminary result exponent is compared to an overflow or underflow threshold value in order to predict whether there is a possibility that an overflow or underflow floating-point exception could occur. Overflow and underflow exceptions are predicted and an exception prediction signal is generated. The exception prediction signals that are generated may be used by data processing system control units, for example, to temporarily halt any parallel processing operations that may be affected by an overflow or underflow floating-point exception.

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Los Altos, CA, United States of America

Ying-wai Ho