Synopsys, Inc.

Springsoft Usa, Inc.

Springsoft, Inc.

Ying-Tsai Chang

Yu-Chin Hsu

Meng-Chyi Lin

Hwa Mao

Kuen-Yang Tsai

Ming-Yang Wang

Tayung Liu

Ryan Zhang

Swey-Yan Shei

Embodiments of the present disclosure relate to a system and method for incremental compilation. The method includes identifying a change to a portion of a circuit design. The circuit design without the change was previously compiled to an FPGA. The method also includes configuring a transactor of the FPGA to simulate the portion of the circuit design with the change and configuring the FPGA to use the transactor to simulate the portion of the circuit design with the change.

Incremental compilation for FPGA-based systems

Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.

Emulation-based functional qualification

Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.

Method and apparatus for versatile controllability and observability in prototype system

A netlist description of a circuit is processed to classify some signals of the circuit as essential signals and to classify all other signals of the circuit as non-essential signals. Thereafter when simulating behavior of the entire circuit in response to input signals supplied over some time interval, a simulator saves first simulation data representing behavior of the circuit's essential signals during the time interval. Thereafter the simulator is programmed to re-simulate behavior of only a selected subcircuit of the circuit during only a selected subinterval of the full time interval based on behavior of essential signals described by the first simulation data. During the re-simulation, the simulator saves second simulation data representing behavior of both essential and non-essential signals of the subcircuit to provide a more complete picture of the behavior of the selected subcircuit during the selected subinterval. Before the initial full-circuit simulation, each signal is classified as an essential signal when its behavior during the full-circuit simulation must be represented by the first simulation data in order to provide sufficient information to program the simulator to re-simulate the behavior any selected subcircuit during any selected subinterval. All other circuit signals are classified as non-essential signals whose behavior need not be represented by the saved first simulation data.

Incremental circuit re-simulation system

Growing community of inventors

Fremont, CA, United States of America

Ying-Tsai Chang