Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying-Min Chou

Shih-Chieh Chang

Wen-Chu Hsiao

Chun-Chieh Wang

Huai-Tei Yang

Yi-Ming Huang

Hsiang-Hsiang Ko

Kei-Wei Chen

Chun Hsiung Tsai

Shiu-Ko JangJian

Ting-Chang Chang

Yi-Fang Pai

Chin-I Liao

Sheng-Wen Yu

Hsiu-Ting Chen

Lai-Wan Chong

Chun-Ju Huang

Mon-Nan How

A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.

Cyclic deposition etch chemical vapor deposition epitaxy to reduce EPI abnormality

A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.

Surface tension modification using silane with hydrophobic functional group for thin film deposition

A semiconductor structure including a semiconductor substrate is provided. The semiconductor substrate includes a surface. A gate structure is provided on the surface. An interface lower than the surface is provided. An epitaxial regrowth region adjacent the gate structure is disposed on the interface. In addition, the epitaxial regrowth region extends over the surface and includes a bottom layer and a cap layer. The activation of the cap layer is lower than that of the bottom layer. Moreover, the bottom layer is lower than the surface and the gate structure. Furthermore, the bottom layer includes a first downwardly-curved edge and a second downwardly-curved edge over the first one. The first downwardly-curved edge is connected with the second downwardly-curved edge at two endpoints. The two endpoints are in contact with the surface of the semiconductor substrate.

Epitaxy in semiconductor structure and manufacturing method thereof

A method of fabricating a FinFET includes at last the following steps. A semiconductor substrate is patterned to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin between the trenches. Insulators are formed in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. A strained material doped with a conductive dopant is formed over portions of the semiconductor fin revealed by the gate stack, and the strained material is formed by selectively growing a bulk layer with a gradient doping concentration.

Fin field effect transistor and method for fabricating the same

A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain region includes: a first epitaxial-grown doped layer of the raised source/drain region in contact with the substrate; a second epitaxial-grown doped layer on the first epitaxial-grown doped layer and including a same dopant species as the first epitaxial-grown doped layer, wherein the second epitaxial-grown doped layer includes a higher dopant concentration than the first epitaxial-grown doped layer and interfacing the gate structure by using a predetermined distance; and a third epitaxial-grown doped layer on the second epitaxial-grown doped layer and including the same dopant species as the first epitaxial-grown doped layer, wherein the third epitaxial-grown doped layer includes a higher dopant concentration than the second epitaxial-grown doped layer.

Semiconductor device and manufacturing method thereof

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes proving a substrate. The substrate includes a gate stack over the substrate and source/drain regions separated by the gate stack. A first dislocation with a first pinch-off point is formed within the source/drain region with a first depth. A second dislocation with a second pinch-off point is formed within the source/drain region at a second depth. The second depth is substantial smaller than the first depth.

Semiconductor integrated circuit with dislocations

A method for fabricating a dual damascene metal gate includes forming a dummy gate onto a substrate, disposing a protective layer on the substrate and the dummy gate, and growing an expanding layer on sides of the dummy gate. The method further includes removing the protective layer, forming a spacer around the dummy gate, and depositing and planarizing a dielectric layer. The method further includes selectively removing the expanding layer, and removing the dummy gate.

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Tainan, Taiwan

Ying-Min Chou