Vlsi Technology, Inc.

Cadence Design Systems, Inc.

Vsli Technology, Inc.

Ying-Meng Li

Sunil V Ashtaputre

Mark R Hartoog

Siu-Tong Hui

Moazzem M Hossain

Jacob Greidinger

Chih-Wei Jim Chang

Louis Chao

So Zen Yao

A method and system of improving signal integrity in integrated circuit designs is disclosed. In some embodiments, signal integrity optimization is conducted in conjunction with detailed routing of an integrated circuit design based upon a global routing plan previously generated for the design.

Method and system for improving signal integrity in integrated circuit designs

The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

Method and apparatus for making integrated circuits by inserting buffers

A method of optimizing the placement of components of an integrated circuit to ensure that all circuit paths will meet their timing criteria, as well as to minimize area and total wire length is disclosed. The method employs a non-constant net weighting distribution along critical paths to encourage a mincut algorithm to place components so that path lengths are minimized as well as the entire nets coupled to paths. The magnitude of weights assigned are commensurate with the slack the path has with respect to its maximum delay constraint, as well as the level of method iteration. Any nets not deemed critical are assigned a minimum capacitance constraint to prevent them from becoming critical as a function of actual placement. Weights assigned to capacitively constrained nets are inversely proportional to the difference between the maximum capacitance allowed and the estimated capacitance of the current placement. A novel manner of estimating the propagation delay along the interconnect of the critical path is implemented. A novel weighting of driver/buffer pairs ensure that the most sensitive nets of the pairs are kept short.

Interactive time-driven method of component placement that more directly

The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

Growing community of inventors

San Jose, CA, United States of America

Ying-Meng Li