Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Ying-Lin Liu

Chung-Hsing Wang

Kai-Yun Lin

Chih Sheng Tsai

Yu-Cheng Lin

Shih-Chang Lin

Chung-Lun Huang

Lin Liu

A memory management circuit, an electronic device and a memory management method are provided. The memory management circuit includes a controller and an address mapping logic. The controller records addresses of available storage spaces within a memory device, wherein a searching logic of the controller stores the addresses in a storage device, and the addresses are queued with a specific order in the storage device. When a computing circuit send a storage request to request for a storage resource, the searching logic obtains at least one address queued in the storage device according to the specific order of the addresses queued in the storage device, to accordingly generate a mapping table, and the address mapping logic performs an address mapping operation upon the storage request according to the mapping table, to allow the computing circuit to utilize the available storage spaces according to the mapping table.

Memory management circuit, electronic device and memory management method

A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Verification of 3D integrated circuits

A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.

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Hsinchu, Taiwan

Ying-Lin Liu