Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying-Lin Chen

Ling-Sung Wang

Chiang-Lang Yen

Chen-Hua Douglas Yu

Yi-Li Hsiao

Jean Wang

Po-Zen Chen

Lawrance Sheu

Yu-Cheng Chang

Chi-An Kao

An apparatus includes a processing chamber having a plasma containing region, a dielectric plate secured on top of the processing chamber, a power source separated from the plasma containing region by the dielectric plate, and a chuck supported within the processing chamber. The chuck is operable and configured to move with respect to the power source.

Apparatus and method to improve uniformity and reduce local effect of process chamber

A adjustable upper coil or electrode for a reaction chamber apparatus useable in semiconductor processing, is constructed so that its shape may be selectively changed or so at least two portions thereof may be selectively driven at different power and/or frequencies. The adjustable upper coil or electrode, therefore, enables the plasma density distribution in the reaction chamber apparatus to be selectively controlled.

Adjustable electrodes and coils for plasma density distribution control

A method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode is deposited over the layer of gate oxide. The gate electrode is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N/H, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

Approach to prevent undercut of oxide layer below gate spacer through nitridation

A new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode such as polyimide is deposited over the layer of gate oxide. The gate electrode and the layer of gate oxide are patterned. A layer of liner oxide is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N /H , reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

Approach to prevent spacer undercut by low temperature nitridation

A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, wherein the underlying component of the composite insulator spacer is comprised of a thin silicon oxide layer obtained via chemical vapor deposition procedures using tetraethylorthosilicate (TEOS), as a source, has been developed. To densify the underlying thin silicon oxide layer an anneal procedure usually performed after implantation of ions used for a lightly doped source/drain region, is delayed and performed after deposition of the thin silicon oxide layer. The anneal procedure is then used for both activation of the lightly doped source/drain ions, and densification of the thin silicon oxide layer. The etch rate of the densified silicon oxide layer, in dilute hydrofluoric acid procedures is now reduced allowing the underlying silicon oxide component, of the composite insulator spacer, to survive subsequent wet clean procedures employing dilute hydrofluoric acid.

Growing community of inventors

Taichung, Taiwan

Ying-Lin Chen