Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

National Cheng-kung University

National Science Council

Ying-Lang Wang

Kei-Wei Chen

Shih-Chieh Chang

Szu-An Wu

Yu-Ku Lin

Kuo-Hsiu Wei

Huicheng Chang

Liang-Yin Chen

Su-Hao Liu

Shiu-Ko JangJian

Kuo-Ju Chen

Yi-Lung Cheng

Chi-Wen Liu

Shih-Tzung Chang

Yu-Sheng Wang

Shih-Chi Lin

I-Chih Chen

Shih-Ho Lin

Jung-Chih Tsao

Jowei Dun

Tang-Kuei Chang

Hsiang Hsiang Ko

Li-Ting Wang

Ting-Chang Chang

Ting-Chun Wang

Chih-Mu Huang

Wen-Yen Chen

Ying-Hao Chen

Wen-Kung Cheng

Hung-Ju Chien

Volume Chien

Chih Hung Chen

Hsi-Kuei Cheng

Miao-Cheng Liao

Hsin-Chi Chen

Chun-Chang Chen

Li-Chieh Wu

Jian-Shin Tsai

Ting-Kui Chang

Chih-Chang Huang

Te-Ming Kung

Ing-Ju Lee

Chia Hsuan Lee

Wen-Ting Chu

Chun-Chieh Wang

Chi-Cherng Jeng

Chia-Cheng Chen

Huai-Tei Yang

Chi-Cheng Hung

Chun-Hung Wu

Wen-Chang Kuo

Jung-Chi Jeng

Tong-Chern Ong

Wei-Ken Lin

Fu-Tsun Tsai

Wen-Hsi Lee

Chun-Che Lin

Chin Kun Lan

Jia-Ming Lin

Chuan-Pu Liu

Hsien-Ping Feng

Fu-Yen Jian

Chung-Shi Liu

Yee-Chia Yeo

Yu-Ting Lin

Chih-Hung Chen

Sheng-Wen Chen

Hung Jui Chang

Min Hao Hong

Chih-Chung Chang

Jun-Nan Nian

Kuan-Chang Chang

Chih-Hung Pan

Wen-Long Lee

Tsung-Ming Tsai

Po-Jen Shih

Yong-En Syu

Li-Yen Fang

Chen-Hua Douglas Yu

Horng-Huei Tseng

Shau-Lin Shue

Syun-Ming Jang Jang

Tien-I Bao

Chun Hsiung Tsai

Ziwei Fang

Chih-Hao Chen

Ching-Hwanq Su

Chung-Long Chang

Chyi-Tsong Ni

Po-Tsun Liu

Fan-Tien Cheng

Lin-June Wu

Chih-Kang Chao

Wei-Jen Lo

Chin-Kun Wang

Chia-Pin Cheng

Chih-Yuan Yang

Guang-Cheng Wang

Tao Cheng

Jane-Bai Lai

A structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The isolation structure is embedded in the substrate. The isolation structure has a bottom surface and a sidewall. The liner layer is between the substrate and the isolation. A first portion of the liner layer in contact with the sidewall of the isolation structure has a nitrogen concentration lower than a second portion of the liner layer in contact with the bottom surface of the isolation structure.

Semiconductor device

A semiconductor structure includes a substrate, a nanowire disposed over the substrate, a metal gate electrode layer and a gate dielectric layer. A dielectric layer is formed on the substrate. The nanowire has a first portion and a second portion. The nanowire has a first portion and a second portion, the first portion of the nanowire comprises a first semiconductor layer and a second semiconductor layer surrounded by the first semiconductor layer, the second portion comprises the second semiconductor layer. The metal gate electrode layer surrounds the first portion of the nanowire. The gate dielectric layer is disposed between the metal gate electrode layer and the nanowire.

Semiconductor structure

The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Metal loss prevention using implantation

Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Source/drain structure

A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Melt anneal source and drain regions

An apparatus includes a first metrology tool configured to measure an initial thickness of a wafer. The apparatus includes a controller connected to the first metrology tool and configured to calculate a polishing time based on a material removal rate, a predetermined thickness and the initial thickness of the wafer. The apparatus includes a polishing tool connected to the controller and configured to polish the wafer for a first duration equal to the polishing time. The apparatus includes a second metrology tool connected to the controller and configured to measure a polished thickness. The controller is configured for receiving the initial thickness from the first metrology tool and the polished thickness from the second metrology tool, updating the material removal rate based on the predetermined thickness, the polishing time and the polished thickness, and calculating an etching time for etching the polished wafer using the polished thickness.

Wafer thinning apparatus having feedback control

A polishing pad includes a pad layer and one or more polishing structures over an upper surface of the pad layer, where each of the one or more polishing structures has a pre-determined shape and is formed at a pre-determined location of the pad layer, where the one or more polishing structures comprise at least one continuous line shaped segment extending along the upper surface of the pad layer, where each of the one or more polishing structures is a homogeneous material.

Polishing pad for chemical mechanical planarization

Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

Thickness sensor for conductive features

In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.

Semiconductor device, method, and tool of manufacture

The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

Electrode structure to improve RRAM performance

Growing community of inventors

Tien-Chung Village, Taiwan

Ying-Lang Wang