Via Technologies, Inc.

Tian Holdings, LLC

Ying-Lang Chuang

Ming-Hsun Hsu

Chu-Yu Hsiao

Chi-Wei Shih

Chung-Heng Chen

A power control circuit for an optical information recording device is disclosed. A power sampling signal from a photodiode is transmitted to a peal envelope acquiring circuit and a bottom envelope acquiring circuit and then sampled and held, which is fed-back to a laser diode driving circuit. The laser diode driving circuit alters a driving signal emitted to the laser diode according to the fed-back signal to adjust the power of the optical signal emitted from the laser diode. Therefore, cost is reduced and the power control circuit is particularly suitable for high-speed recordable optical disk drive.

Power control circuit for optical information recording device

A signal bounce inhibiting device and a signal bounce inhibiting method are provided for preventing power/ground bounce resulting from simultaneous switching output. The signal bounce inhibiting device includes an electric level toggling circuit and an electric level recovering circuit. The electric level toggling circuit receiving an internal signal of the first chip, and toggling the internal signal into a first output signal in response to a first toggling control signal. The electric level recovering circuit receiving the first output signal, and recovering the first output signal into the internal signal required by a second chip in response to a first recovering control signal.

Simultaneous switching output bounce reduction device and method

A system and method for upgrading data transmission performance under programmed input/output (PIO) mode is disclosed. In one embodiment, a PIO accelerating device is established in an IDE controller for handling data transmissions concerned with read/write operations after taking over associated control right from processing unit. A counter is configured in the PIO accelerating device for varying its stored content followed by a predetermined sequence in responsive to the input pulses of a system clock. A timing signal generator is also established in the PIO accelerating device for issuing signals directed to the IDE device and the buffer in the IDE controller for activating associated data transmission operations while the stored content reaches to a predetermined threshold. Optimal performance to data transmission under IO mode 4 of the PIO mode can be achieved by employing the disclosed hardware configuration.

System and method for data transmission using PIO accelerator device in an IDE controller

For generating a delay signal, a series of source signals based on the same high frequency signal are first provided. Every adjacent two of the source signals have a phase difference of a certain clock unit therebetween. A first and a second output signals are then generated on the basis of the plurality of source signals at a first and a second time points selected as desired. The first and the second output signals are processed by a logic operation to obtain the accurate and adjustable delay signal. For obtaining the first and the second output signals, the source signals are duplicated at first, and then respectively processed in response to respective clock signals.

Method and device for generating delay signal

A device and a method are used for generating a selection signal provided for a multiplexing circuit. The multiplexing circuit generates an output signal from a plurality of source signals in response to the selection signal. The device includes an operational circuit and a toggle control circuit. The method includes steps of: performing an OR operation of the plurality of source signals to obtain an operational output signal; and latching the operational output signal in an active low manner in response to a selection command to obtain the selection signal. By prohibiting the selection signal from toggling when any of the plurality of source signals is at an output-enabled state, the accuracy of the selection signal can be improved.

Method and device for generating selection signal with improved accuracy

A device for recognizing power sources and associated method are provided. The device for recognizing power sources comprises two voltage-dividing devices. Each of the voltage-dividing devices is coupled to receive native power, and outputs the part of the voltage of the native power. According to the method, an output end of one voltage-dividing device is coupled to a signal end of the controller, and an output end of the other voltage-dividing device is coupled to the other signal end of the controller. When the native power exists, both of the above-mentioned signal ends are in a high voltage level. On the other hand, when native power does not exists, both of the above-mentioned signal ends are at a low voltage level. The power source of the hardware device and the value of the native power can be exactly recognized according to the voltage levels of both signal ends.

Device for recognizing power sources and associated method

A generating a digital wave apparatus is provided. The period of a basic clock signal is divided into a plurality of time points, and the level of the highly accurate digital wave is toggled at these time points. The apparatus comprises a delay phase lock loop, for generating a plurality of delayed clock signals according to the basic clock signal; a first multiplexer and a second multiplexer for outputting one of the delayed clock signals according to a first select signal and a second select signal, respectively; a first edge-triggered flip-flop and a second edge-triggered flip-flop for receiving the output signals of the first multiplexer and the second multiplexer respectively; and a logic gate for outputting the digital wave according to the outputs of the first and the second edge-triggered flip-flops. The digital wave is toggled according to the first select signal, and further toggled according to the second select signal. The apparatus of the invention uses the low frequency clock signal to generate a highly accurate digital wave, and can save cost in comparison with the conventional apparatus that uses the high frequency clock signal.

Digital wave generating apparatus and the method thereof

A testing device for checking a clock signal generated by a clock pulse generating circuit. The clock pulse generating circuit outputs a clock signal and a multiplied clock second signal. The testing device includes a reset circuit, a dividing unit and a mask circuit. The reset circuit receives a first reset signal and the clock signal and then generates a second reset signal synchronous with the clock signal. The second reset signal controls the dividing unit and the mask circuit. Inside the dividing unit, the multiplied clock signal is divided by an integral multiple to produce a divided clock signal. The divided clock signal is then passed to the mask circuit where uncertain portions of the third signal are blanketed to produce a masked clock signal. The masked clock signal is sent to a tester where cycle width of the masked clock signal is measured and first reset signal is sent to the reset circuit.

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Kaohsiung, Taiwan

Ying-Lang Chuang