Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying Hsin Lu

Ching-Hwanq Su

Ru-Shang Hsiao

Pin Chia Su

Ling-Sung Wang

I-Shan Huang

Pohan Kung

Ying Ming Wang

Ru-shang Hsiao

A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

Metal gate structures and methods of fabricating the same in field-effect transistors

The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

Circuit structure with gate configuration

A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

Gate electrode having a work-function layer including materials with different average grain sizes

A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.

Gate structure of semiconductor device and method of forming same

A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

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Tainan, Taiwan

Ying Hsin Lu