Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying-Ho Chen

Syun-Ming Jang Jang

Chen-Hua Douglas Yu

Tsu Shih

Jih-Churng Twu

Wen-Chih Chiou

Yu-Jen Shen

Yung-Cheng Lu

Weng Chang

Shen-Nan Lee

Jui-Yu Chang

Tzu-Jen Chou

Shau-Lin Shue

Tien-I Bao

Feng-Cheng Yang

Teng-Chun Tsai

Chih-Wei Wu

Chung-Long Chang

Chia-Jung Hsu

Chu-Yun Fu

Ying-Tsung Chen

Tzu-Hsiang Hsu

Tung-Ching Tseng

Yu-Ting Yen

Chia-Ming Yang

Shu-Wei Hsu

Hao-Yun Cheng

Chunshing Chen

Hung Lo

Ming-Hsing Tsai

William Weilun Hong

Tien-Chen Hu

Kao-Feng Liao

Shwangming Jeng

Chia-Che Chung

Chuan-Ping Hou

Chin-Hsin Peng

Wen-Jye Tsai

Cheng Hsun Chan

Bi-Trong Chen

Chi-Wei Chung

Jin-Yiing Song

Jian-Lin Hwang

Jih-Churng Jwu

Chuang-Ping Hou

In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Methods of forming semiconductor devices

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.

Replacement gate process for semiconductor devices

Semiconductor device and method

A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.

Semiconductor device including fin FET and manufacturing method thereof

A planarization method includes at least two steps. One of the steps is to implant at least one impurity into a wafer to form a polish stop layer in the wafer. The other one of the steps is to polish a top surface of the wafer until reaching the polish stop layer.

Planarization method, method for manufacturing semiconductor structure, and semiconductor structure

Semiconductor device including Fin FET and manufacturing method thereof

The present disclosure relates to a wafer cleaning module for post CMP processes that reduces defects (e.g., watermarks, deposited particles) on a substrate, and an associated method. In some embodiments, the wafer cleaning module has a cleaning tank that may receive a semiconductor substrate within a cleaning medium. A pusher is may vertically move the semiconductor substrate from a starting position within the cleaning tank to an ending position. A position sensor may determine a position of the semiconductor substrate relative to a meniscus of the cleaning medium. Based upon the determined position, a control unit is may adjust a location of the starting position to a predetermined distance below the meniscus.

Wafer cleaning module

A system for use in manufacturing semiconductor devices, is provided. The system includes an electrochemical processing tool and an image sensor. The electrochemical processing tool includes an electrode located at a central region of a platen. The electrode is adapted for contacting a wafer workpiece during certain processing of the wafer workpiece using the tool. At least part of the electrode is viewable from above the platen when the electrochemical processing tool is operably assembled. The image sensor is capable of capturing an image of the viewable part of the electrode. The image sensor is positioned above the platen. The image sensor is adapted to be aimed at the electrode when an image of the electrode is to be taken with the image sensor.

Image sensor system for monitoring condition of electrode for electrochemical process tools

A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.

Polymeric particle slurry system and method to reduce feature sidewall erosion

A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.

Scratch reduction for chemical mechanical polishing

A chemical-mechanical polishing (CMP) process for the manufacturing of semiconductor devices is disclosed. The process includes removing a first portion of a first layer of interconnect materials using a first platen and a first slurry, removing a second portion of the first layer using a second platen and a second slurry, removing a first portion of a second layer of the interconnect materials using a second platen and a third slurry, and removing a second portion of the second layer using a third platen and a fourth slurry.

Chemical mechanical polishing process for manufacturing semiconductor devices

An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.

Chemical mechanical polishing process with reduced defects in a copper process

Growing community of inventors

Taipei, Taiwan

Ying-Ho Chen