Bolb Inc.

Pure Storage, Inc.

Oracle International Corporation

Kla-tencor Technologies Corporation

Kla Tencor Corporation

Ying Gao

Jianping Zhang

Ling Zhou

Boris Feigin

Hari Kannan

Jeffrey R Doering

Igor Ostrovsky

Jeffrey Vincent Tofano

Huazhong Deng

Alexander Lunev

Robert H Lee

Gopalan Arun

Gary Janik

Svitlana Tumanova

Xiao Liu

John Colgrove

Ronald S Karr

Cuong Duy Le

Matthew D Fleming

Faissal Sleiman

Bin Zhang

Alex Lunev

Hailun Yang

Peter E Kirkpatrick

Moshe Sarfaty

Hidong Kwak

Johannes D De Veer

Yu Liu

Sankara Vaideeswaran

Janis Stipins

Guangyu Shi

Wei You

Khushboo Bhatia

Nirmalya Sen

Vicky Cao

Raghuram Kudaravalli

Jintao Shen

Peter Gordon

Timothy Meyer

Shengda Ding

Richard Troxell, Iii

A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.

Storage system with multiple write paths

An apparatus has a current spreading base with an n-contact. The current spreading base has a small n-type resistivity to promote lateral electron flow. A current spreading cap is on top of the current spreading base. The current spreading cap has a large n-type resistivity to suppress vertical electron flow and promote lateral electron flow. An active region is on top of the current spreading cap. A p-type structure is on top of the active region with a p-contact. Sheet resistanceof the current spreading base is experimentally established, the half width xof a mesa is selected and the current spreading cap thickness his selected to collectively promote uniform current injection into the active region.

Current spreading structure for light-emitting diode

A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.

Dynamic migration techniques

A data segment to be written to a set of storage devices is identified, wherein at least one storage device of the set of storage devices has a first allocation unit size that is larger than a second allocation unit size of other storage devices of the set of storage devices. A first subsegment having a first subsegment height corresponding to the second allocation unit size is mapped across the set of storage devices. A second subsegment having a second subsegment height that is a first difference between the first allocation unit size and the second allocation unit size is mapped across a first subset of the set of storage devices. A third subsegment having a third subsegment height that is a second difference between the second allocation unit size and second subsegment height is mapped across a second subset of the set of storage devices.

Intelligent subsegment formation in a heterogeneous storage system

A die-aware scheduler that has a hierarchical queue is suitable for use in data storage systems. The hierarchical queue includes a priority queue, a die queue, a write queue and a power token queue, and may also include an admission queue. The die queue, the write queue and the power token queue have a width and lanes corresponding to dies in solid-state storage. The hierarchy of queues has dynamic adjustability of a ratio relating to handling queue items in the hierarchy of queues, to optimize latency and throughput.

Die-aware scheduler

A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.

Performing low latency operations using a distinct set of resources

The present application discloses a ceiling-mount air disinfector, i.e., an air disinfection troffer, including: a housing; a first air outlet and a first air inlet respectively near two opposing ends of a side of the housing; a filter covering the first air inlet; a cross flow fan located near the first air outlet, and an air disinfection apparatus disposed in the housing including an ultraviolet disinfection mechanism and an air rectifying chamber, said air rectifying chamber including a plurality of air ducts configured in parallel. In operation, ultraviolet light and air flow are introduced into the air ducts, traveling toward each other along a long side of the air ducts so that maximized air-light interaction time is achieved for the best disinfection efficacy.

Air disinfection troffer

A storage system is provided. The storage system include a primary storage node that includes a primary processing device. The primary storage node is communicatively coupled to a secondary storage node. The secondary storage node includes a secondary processing device and a set of non-volatile memory modules. The primary processing device is to identify one or more storage operations to be performed on the set of non-volatile memory modules of the secondary storage node and transmit one or more instructions to the secondary storage node to perform the one or more storage operations, the one or more storage operations performed by the secondary processing device.

Device host operations in a storage system

A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes determining that a size of a buffer of a storage system should be adjusted. The storage system comprises a non-volatile random-access memory (NVRAM), single level cell (SLC) flash memory, and quad level cell (QLC) flash memory. The buffer of the storage system comprises one or more of the NVRAM and a portion of the SLC flash memory. The method also includes adjusting the size of the buffer of the storage system to a first size.

Dynamic buffer for storage system

A light emitting device with on-chip optical power readout includes a light emitting mesa and a light detecting mesa formed adjacent to each other on the same substrate of a chip, and a portion of the light emitted from the light emitting mesa is transmitted to the light detecting mesa at least through the substrate. The light emitting mesa and the light detecting mesa have exactly the same epitaxial structure and can be electrically isolated from each other by an insulation layer, or an airgap formed therebetween, or by ion implantation. The light emitting mesa and the light detecting mesa can also share an n-type structure and a common n-electrode while having their own p-electrode, respectively.

Light-emitting device with optical power readout

A patterned substrate for light emitting diode includes a plurality of nodes and links protruding from a base plane of the substrate and base areas on the substrate, each pair of adjacent nodes is connected by a corresponding link, respectively. The nodes and links also can be concave nodes and concave links cutting into a surface of the substrate, each pair of adjacent concave nodes is connected by a corresponding concave link, respectively.

Patterned substrate for light-emitting diode

A storage system has a first memory, a second memory that include solid-state storage memory, and a processing device. The processing device is to select a mode for each portion of data to be written. Selection of the mode is based at least on size of the portion of data. Selection of the mode is from among modes that include a first mode of writing the portion of data in mirrored RAID form to the first memory for later transfer from the first memory to the second memory, a second mode of writing the portion of data in parity-based RAID form to the first memory for later transfer from the first memory to the second memory, and a third mode of writing the portion of data to the second memory, bypassing the first memory. The processing device is to handle portions of data to be written according to such selection.

Storage system with selectable write modes

A storage system has a first storage and a second storage. The first storage has a first plurality of blades with first computing resources, first RAM resources and first solid-state storage resources. The second storage has second plurality of blades with second computing resources, second RAM resources and second solid-state storage resources. The first computing resources and the second computing resources cooperate to determine on which blades of the first and second pluralities of blades, and in which storage of the first and second storage, to perform compute processes and memory controller processes, using which of the first and second computing resources. The first computing resources and the second computing resources cooperate to determine on which blades of the first and second pluralities of blades and in which storage of the first and second storage to use which of the first and second RAM resources and to use which of the first and second solid-state storage resources, in service of performing the compute processes and the memory controller processes for data and metadata accesses.

Optimizing storage system upgrades to preserve resources

A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.

Write path selection

Selectable write paths with different formatted data

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San Jose, CA, United States of America

Ying Gao