Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying-Chih Hsu

Alan S Roth

Eric Soenen

Wen-Shiang Liao

Jui-Cheng Huang

Chuei-Tang Wang

Justin Shi

Chih-Yuan Chang

Mei-Chen Chuang

Chia Liang Tai

Chih-Lin Chen

Wen-Shen Chou

Stefan Rusu

Tze-Chiang Huang

Mei Hsu Wong

Nick Samra

Haohua Zhou

Justin Gaither

Guang-Cheng Wang

Paul Ranucci

Chia-Chun Chang

Wei-Tao Shaw

Mu Wei Lee

A method of manufacturing a semiconductor device is provided. A permalloy device is received. An interposer die is formed. A conductive coil is formed over a substrate, and the conductive coil includes a bottom metal layer over the substrate, a middle metal layer and a top metal layer interconnected to each other. The permalloy device is disposed in the middle metal layer through a pick and place operation before forming the top metal layer of the conductive coil. A semiconductor die is bonded to the interposer die. The permalloy device has a polygonal ring shape wrapped with the conductive coil.

Semiconductor package device with integrated inductor and manufacturing method thereof

A semiconductor package includes an array of through-substrate-via (TSV) structures comprising a number (O) of TSV structures, wherein the array comprises a number (M) of active TSV structures; a number (N) of contact structures, the contact structures comprising a plurality of pairs configured to receive an input test signal and provide an output test signal, respectively; and a plurality of binary-tree branches, each of the plurality of binary-tree branches electrically coupling a first one of the active TSV structures to a second one of the active TSV structures and a third one of the active TSV structures.

Semiconductor packages with through via structures and methods for testing the same

A power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.

Power module

A semiconductor device includes a method of manufacturing a semiconductor device. The method includes forming an interconnect structure. In some embodiments, the forming of the interconnect structure includes forming a first patterned layer over a substrate, attaching a die attach film (DAF) to a permalloy device and transporting the permalloy device to the first patterned layer through a pick and place operation, forming a second patterned layer in the same tier as the permalloy device, and bonding a semiconductor die to the interconnect structure. In some embodiments, the second patterned layer is aligned with the first patterned layer, forming a third patterned layer over the second patterned layer and the permalloy device. In some embodiments, the first patterned layer, the second patterned layer and the third patterned layer collectively form a coil winding around the permalloy device.

A package includes first and second redistribution structures, a die, a permalloy structure, a molding material and a plurality of through vias. The first redistribution structure includes a first metal pattern. The die is disposed over the first redistribution structure. The molding material is disposed over the first redistribution structure and surrounds the die and the permalloy structure. The second redistribution structure is disposed over the die, the permalloy structure and the molding material, and includes a second metal pattern. The through vias penetrate the molding material and connects the first metal pattern to the second metal pattern. The permalloy structure includes a first member and a second member isolated from the first member, the first member and the second member are surrounded by the plurality of through vias and sandwiched between the first metal pattern and the second metal pattern. A method for forming a package is also provided.

Power management semiconductor package and manufacturing method thereof

A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Power delivery for multi-chip-package using in-package voltage regulator

A semiconductor device includes a semiconductor substrate, an interconnect structure, and a permalloy device. The interconnect structure is disposed over the semiconductor substrate. The interconnect structure includes a conductive coil. The conductive coil includes horizontally-extending metal lines, and vertically-extending vias electrically connecting the metal lines. The permalloy device is disposed in the interconnector structure and wound around by the conductive coil and insulated by the conductive coil, wherein the permalloy device and the conductive coil in combination define an inductor, and the permalloy device serves as a magnetic core of the inductor.

A DC-DC converter and a DC-DC converter operation method are provided. The DC-DC converter includes a power stage, an error amplifier, a pulse width modulation (PWM) generator, and a gate controller. The power stage includes a first transistor and a second transistor. The voltage dividers are configured to perform a voltage division on a first node of the power stage and a second node to generate a first voltage and a second voltage. The first node is an output node of the DC-DC converter and the second node is a node between the first transistor and the second transistor of the DC-DC converter. The comparator is configured to compare the first voltage and the second voltage to generate a turn-on time signal of the first transistor according to a comparison result.

DC-DC converter and DC-DC converter operation method

A power converter module includes a ground terminal, an input voltage terminal confirmed to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.

A current balance circuit including a current sensing front end for sensing an output signal from each of a plurality of switching regulators and a current sensor for receiving the sensed output signal and converting the sensed signal into a sensed current signal. The current balance circuit further includes a current averaging circuit for receiving the sensed output signals and determining an average current output for the plurality of switching regulators and a current difference circuit for receiving the average current value and the sensed current signals and determining a current difference for each of the plurality of switching regulators. A calibration circuit is included for receiving the current differences and calculating a calibration value corresponding to each of the plurality of switching regulators which provides an indication of how to adjust a current output of the plurality of switching regulators to balance the current across the plurality of switching regulators.

Current balance circuit

An inductor is formed in an IC device packaging structure. The structure includes an encapsulating material, with a ferromagnetic core in the encapsulation material. A plurality of metal layers are provided in the encapsulation material forming an inductor coil extending around the ferromagnetic core so as to form an inductor.

Packaging layer inductor

A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.

Heat transfer structures and methods for IC packages

An integrated circuit (IC) package structure includes an electrical signal path, a low thermal resistance path and a substrate that includes a first device and a second device. The first device and the second device are part of an IC chip. The electrical signal path is from the first device to a top surface of the IC chip. The low thermal resistance path extends from the second device to the top surface of the IC chip. The low thermal resistance path is electrically isolated from the electrical signal path. The second device is thermally coupled to the first device by a low thermal resistance substrate path.

A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.

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Hsinchu, Taiwan

Ying-Chih Hsu