Megica Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Qualcomm Incorporated

Airoha Technology Corporation

Megit Acquisition Corp.

Ying-Chih Chen

Mou-Shiung Lin

Jin-Yuan Lee

Chiu-Ming Chou

Blanka Magyari-Kope

Hsin-Jung Lo

Shih-Hsiung Lin

Shun-Tien Lee

Shin-Ge Lee

Chun-Hsing Lee

Cherng-Shiun Wu

Sai-Hooi Yeong

Yu-Ming Lin

Chung-Te Lin

Bo-Feng Young

Chun-Chieh Lu

Yi-Ming Chen

Tzer-Min Shen

Chien-Chun Lu

Yen Chu

Yao-Ling Cheng

Yu-Chuan Shih

Hsien-Huan Chiu

Qing Shi

Kuo-Chang Chang

Jen-Chan Huang

Min-Yu Lin

A device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm.

Semiconductor device, ferroelectric capacitor and laminated structure

A semiconductor device includes a first electrode layer, a ferroelectric layer, and a second electrode layer. A material of the ferroelectric layer comprises a ferroelectric material doped with a first dopant and a second dopant different from the first dopant, and the first dopant comprises cerium. The ferroelectric layer is disposed between the first electrode layer and the second electrode layer.

Semiconductor devices having ferroelectric tunnel junction structure

A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.

Semiconductor devices including FTJ structure

A semiconductor device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer includes SrRuO, InGaZnO (IGZO) or LaSrMnO.

A semiconductor package includes a first die, a second die, and a hybrid-type adhesive. The second die is stacked on the first die through the hybrid-type adhesive. The hybrid-type adhesive includes a conductive adhesive and a non-conductive adhesive. The conductive adhesive is disposed between the non-conductive adhesive and the first die. The non-conductive adhesive is disposed between the conductive adhesive and the second die.

Semiconductor package using hybrid-type adhesive

A semiconductor device includes a substrate, a gate stack over the substrate, a channel layer over the gate stack, and a source/drain electrode. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The source/drain electrode is formed on the channel layer and disposed on sides of the gate stack.

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Method of wire bonding over active area of a semiconductor circuit

A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Stacked chip package with redistribution lines

A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes.

Over-passivation process of forming polymer layer over IC chip

Growing community of inventors

Hsinchu, Taiwan

Ying-Chih Chen