Mstar Semiconductor, Inc.

Ying-Chieh Chiang

Shih-Chieh Yen

Chien-Sheng Chen

Chiung Hung Chang

Chien-Shan Chiang

Li-Wei Sheng

A searching method for finding a target location in a variable space is provided. The variable space is constructed by a set of variables and has multiple sub-spaces. The target location renders an output result of a wireless communication system to satisfy a target value. The search method includes steps of: providing the set of variables; identifying a target sub-space where the target location is located from the sub-spaces; obtaining a plurality of gradients of the output result at a predetermined location from the target sub-space, each of the gradients corresponding to a direction of change; and selecting one from the directions of change according to the gradients, and changing values of the set of variables according to the selected direction of change to find the target location.

Search method for wireless communication system

A signal processing apparatus includes: a signal conversion circuit, for performing a signal conversion operation on a reception signal to generate a first output signal according to a first clock signal, and performing the signal conversion operation on the reception signal according to a second clock signal to generate a second output signal; an amplitude adjustment circuit, coupled to the signal conversion circuit, for calculating an amplitude value of the reception signal according to the first output signal, and accordingly adjusting an amplitude of the reception signal; and a phase adjustment circuit, for adjusting a phase of the second clock signal according to the second output signal.

Signal processing apparatus and associated method

A decoding apparatus is disclosed. The decoding apparatus is applied to a data signal comprising a plurality of bits. A plurality of sampled data is generated by sampling the data signal. Each of the bits has a same cycle. The decoding apparatus comprises a calculating module and a determining module. When the calculating module sets a first interval and a second interval in the cycle of a specific bit, the calculating module generates a first count according to the sampled data in the first interval corresponding to a first logic level and generates a second count according to the sampled data in the second interval corresponding to a second logic level. The determining module determines a digital logic value of the specific bit.

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Hsinchu Hsien, Taiwan

Ying-Chieh Chiang