Mediatek Corporation

Realtek Semiconductor Inc.

Epistar Corporation

Auo Corporation

Ying-Chieh Chen

Mei-Li Yu

Yu-Lan Lo

De-Shan Kuo

Po-Shun Chiu

Shih-Chin Lin

Shu-Yi Kao

Jhih-Jheng Yang

Jian-Huei Li

Zi-Jin Lin

Jiun-Ru Huang

Yu-Sheng Lin

Chih-Wei Chen

Pei-Kuei Tsung

Yao-Sheng Wang

Yung-Hsiang Lan

Chih-Wen Goo

Ting-Hsiung Wang

Shih-Che Chen

Chien-Chih Wang

Hsin-Chang Lin

Cheng-Lung Jen

I-Hsuan Lu

Tsung-Shian Huang

Yi-Fu Ou

Jen Cheng Lung

Huang Tsung-Shian

A circuit simulation method includes the following operations: performing Monte Carlo simulations in parallel according to a first netlist file and process model data, in order to generate a performance simulation result, in which the first netlist file is configured to indicate a basic circuit in a circuitry; selecting component parameters lower than a predetermined yield rate according to the performance simulation result; and determining whether an estimated yield rate of the circuitry meets the predetermined yield rate according to the component parameters.

Circuit simulation method and circuit simulation system

Disclosed are a display panel and a pixel circuit thereof. The pixel circuit includes a driving transistor, a data write-in circuit, a compensation circuit, a voltage control circuit, a light-emitting switch, and a light-emitting element. The driving transistor receives a power supply voltage. The data write-in circuit receives a first scanning signal, an emission signal, and a write-in data signal, stores the write-in data signal, and provides the write-in data signal to a control end of the driving transistor. The compensation circuit has a first switch and a second switch coupled to a relay end and controlled by a second scanning signal. The voltage control circuit adjusts a voltage difference between the control end of the driving transistor and the relay end. The light-emitting switch is coupled between a second end of the driving transistor and the light-emitting element, and is controlled by the emission signal.

Display panel and pixel circuit thereof

A pixel circuit includes a driving transistor, a storage capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor. A first end of the driving transistor is electrically coupled to a system high voltage terminal. The driving transistor is configured to control a driving current supplied to a light emitting element. A first end of the storage capacitor is electrically coupled to a control end of the driving transistor. A first end of the first transistor is electrically coupled to a second end of the storage capacitor, and a second end of the first transistor is configured to receive a data signal. When the first transistor is turned on according to the first control signal, the storage capacitor resets a voltage at the control end of the driving transistor, by a capacitive coupling effect, according to a change in voltage of the data signal.

Pixel circuit for lower power consumption

Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.

AI frame engine for mobile edge

A graphics system includes an effect engine and a graphics pipeline. The graphics pipeline performs pipeline operations on graphical objects in a frame. The graphics pipeline includes at least a fragment shader stage. An application programming interface (API) provides an instruction that specifies a subset of the graphical objects in the frame for the effect engine to execute. When detecting the instruction, the graphics pipeline invokes the effect engine to perform a predefined set of graphics operations on the subset of the graphical objects in the frame. The predefined set of graphics operations has a higher computational complexity than the pipeline operations.

Hybrid rendering mechanism of a graphics pipeline and an effect engine

Aspects of the disclosure provide a device for processing frames with aliasing artifacts. For example, the device can include a motion estimation circuit, a warping circuit coupled to the motion estimation circuit, and a temporal decision circuit coupled to the warping circuit. The motion estimation circuit can estimate a motion value between a current frame and a previous frame. The warping circuit can warp the previous frame based on the motion value such that the warped previous frame is aligned with the current frame and determine whether the current frame and the warped previous frame are consistent. The temporal decision circuit can generate an output frame, the output frame including either the current frame and the warped previous frame when the current frame and the warped previous frame are consistent, or the current frame when the current frame and the warped previous frame are not consistent.

Disclosed is an IC voltage determining method including: executing a static timing analysis according to a circuit design to obtain data of a critical path and then generating a netlist; executing a circuit parameter simulation and Monte Carlo simulation with the netlist according to a regular voltage and prescribed parameters to obtain a circuit parameter reference value and a variance of circuit parameter values; executing an adaptive voltage scaling analysis according to a voltage range to obtain a voltage-versus-parameter relation indicative of the number of times that each of circuit parameter deviations that are respectively associated with predetermined voltages within the predetermined voltage range is of the variance; and testing an IC according to the regular voltage to obtain a circuit parameter test value and determining the IC voltage according to the voltage-versus-parameter relation and a difference between the circuit parameter test value and the circuit parameter reference value.

Method for determining IC voltage and method for finding relation between voltages and circuit parameters

A graphics system includes an effect engine, which executes a predefined set of graphics operations having a higher computational complexity than pipeline operations. The graphics system further includes a graphics pipeline operative to perform the pipeline operations on graphical objects in a frame. The effect engine is operative to execute the predefined set of graphics operations on a subset of the graphical objects in the frame. One or more buffers are operative to receive pixels of the frame for display. The frame includes the graphical objects operated on by the graphics pipeline and the subset of the graphical objects operated on by the effect engine.

The present disclosure discloses a glitch occurring point detection method to detect at least one glitch occurring point in an under-test circuit that includes the steps outlined below. An IC design file is retrieved to further retrieve a plurality of input nodes, at least one output node and a plurality of power nodes corresponding to the under-test circuit in the IC design file. Signals are fed to the input nodes and the power nodes such that a DC analysis is performed on a plurality of internal circuit nodes in the under-test circuit and a plurality of candidate floating points that do not have any charging or discharging path connected thereto are retrieved according to the DC analysis. Each of the candidate floating points capable of triggering the output node during the operation of the under-test circuit are determined to be the glitch occurring point.

Glitch occurring point detection apparatus and method

A method of manufacturing a light-emitting device is disclosed. The method includes providing a light-emitting diode wafer, including a substrate and a semiconductor stack on the substrate, wherein the semiconductor stack has a lower surface facing the substrate and an upper surface opposite to the lower surface; providing a first laser on the light-emitting diode wafer and irradiating the light-emitting diode wafer from the upper surface to form a plurality of scribing lines on the upper surface; providing an etching process; providing and focusing a second laser on an interior of the substrate to form one or a plurality of textured areas in the substrate; and providing force on the light-emitting diode wafer to separate the light-emitting diode wafer into a plurality of light-emitting diode chips along the plurality of scribing lines.

Manufacturing method of light-emitting device

A simulation method for a mixed-signal circuit system includes: detecting a plurality of registers and a clock signal included in the mixed-signal circuit system; performing a timing analysis converting operation upon a circuit block coupled between any two register of the plurality of registers to obtain a converted circuit system; and performing a Static Timing Analysis operation upon the converted circuit system; wherein when the circuit block is convertible into a combinational circuit block, the timing analysis converting operation includes: converting the circuit block to the combinational circuit block, wherein the combinational circuit block is logic gate-level.

Simulation method for mixed-signal circuit system and related electronic device

A manufacturing method of light-emitting device is disclosed. The method includes providing an LED wafer comprising a substrate and a semiconductor stack formed on the substrate, wherein the semiconductor stack has a lower surface facing the substrate and an upper surface opposite to the lower surface; providing a first laser to the LED wafer and irradiating the LED wafer from the upper surface to form a plurality of scribing lines on the upper surface; providing and focusing a second laser on an interior of the substrate to form a plurality of textured areas in the substrate; and providing force on the LED wafer to separate the LED wafer into a plurality of LED chips.

A graphics processing unit (GPU) renders graphical objects into a group of pixels and stores the pixels in an on-chip buffer on the same chip as the GPU. Each pixel has an alpha value that indicates transparency of the pixel. The GPU reads the alpha value of each pixel from the on-chip buffer. According to alpha values of the group of pixels, the GPU generates an alpha hint in the system memory for the group of pixels. The alpha hint represents an aggregate of the alpha values of the group of pixels. The GPU then stores the group of pixels into a frame buffer in the system memory.

Bandwidth efficient method for generating an alpha hint buffer

A computer program product stored in a non-transitory storage device of an integrated circuit (IC) timing analysis device includes: a netlist reading module for reading a netlist of an integrated circuit; a signal path analysis module for analyzing signal paths of a clock signal to generate a simplified netlist of the integrated circuit; a clock delay calculating module for calculating clock delays of the clock signal respectively corresponding to the signal paths.

Computer program product for timing analysis of integrated circuit

A light-emitting device is disclosed. The light-emitting diode device includes a substrate, comprising an upper surface, a lower surface and a plurality of side surfaces; and a semiconductor stack formed on the upper surface of the substrate; wherein the plurality of side surfaces comprises: a first region, adjacent to the upper surface and having a first surface roughness; a second region, comprising one or a plurality of textured areas substantially parallel to the upper surface and/or the lower surface in a side view, wherein the textured area is composed of a plurality of textured stripes and has a second surface roughness; and a third region, having a third surface roughness and being between the first region and the second region, and/or between the plurality of textured areas; wherein the first surface roughness is smaller than the second surface roughness, and the third surface roughness is smaller than the first surface roughness.

Growing community of inventors

Hsinchu, Taiwan

Ying-Chieh Chen