Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solar Ltd.

Vanguard International Semiconductor Corporation

Ying-Chen Chao

Jin-Yuan Lee

Chih-Jen Yang

Edward F Teng

Ting-Hwang Lin

Shih-Shiung Chen

Ming-Fa Chen

Ho-Ku Lan

Syun-Ming Jang Jang

Chung-Long Chang

Chih-Heng Shen

Chia-Hsiang Chen

Yuan-Ko Hwang

Huan Chi Tseng

Ming-Chu King

Sen-Shan Yang

Chung-An Lin

John C-s Wei

Yi-Lin Sun

Wen-Jui Fu

Keng-Hui Liao

Lung-Hsiang Chuang

Kuo-Jui Hsiao

Yi-Dong Yan

Jhy-Sheng Sheu

John Chih-Shih Wei

Wi William Lee

An apparatus for forming a solar cell includes a housing defining a vacuum chamber, a rotatable substrate support, at least one inner heater and at least one outer heater. The substrate support is inside the vacuum chamber configured to hold a substrate. The at least one inner heater is between a center of the vacuum chamber and the substrate support, and is configured to heat a back surface of a substrate on the substrate support. The at least one outer heater is between an outer surface of the vacuum chamber and the substrate support, and is configured to heat a front surface of a substrate on the substrate support.

Method and system for forming absorber layer on metal coated glass for photovoltaic devices

Apparatus for forming a solar cell comprises a housing defining a chamber including a substrate support. A sputtering source is configured to deposit particles of a first type over at least a portion of a surface of a substrate on the substrate support. An evaporation source is configured to deposit a plurality of particles of a second type over the portion of the surface of the substrate. A cooling unit is provided between the sputtering source and the evaporation source. A control system is provided for controlling the evaporation source based on a rate of mass flux emitted by the evaporation source.

Apparatus and method for forming thin films in solar cells

A method and apparatus for forming a solar cell. The apparatus includes a housing defining a vacuum chamber and a rotatable substrate apparatus configured to hold a plurality of substrates on a plurality of surfaces wherein each of the plurality of surfaces are disposed facing an interior surface of the vacuum chamber. A first sputtering source is configured to deposit a plurality of absorber layer atoms of a first type over at least a portion of a surface of each one of the plurality of substrates. An evaporation source is disposed in a first subchamber of the vacuum chamber and configured to deposit a plurality of absorber layer atoms of a second type over at least a portion of the surface of each one of the plurality of substrates. A first isolation source is configured to isolate the evaporation source from the first sputtering source.

Apparatus and method for producing solar cells

An accelerated thermal stress cycle test which can be conducted in a significantly reduced test time compared to the conventional test is provided. The test is carried out in a cluster of reaction chambers that includes a CVD chamber and a cool-down chamber such that a pre-processed wafer can be heated from room temperature to at least 350&deg; C. in an inert gas in about 2 min., and then cooled down to not higher than 70&deg; C. in a cool-down chamber in less than 30 sec. The heating and cooling steps can be repeated between 3 and 7 times to reveal any defect formation caused by the thermal stress cycle test. Typical defects are metal film peeling from insulating dielectric material layer or void formation.

Accelerated thermal stress cycle test

A test sample with a film and an underlying substrate representing part of a semiconductor wafer is prepared for a stud pull test by a process that includes maintaining the sample in boiling salt water for a few hours. When an epoxy stud is attached to the film of the sample and the clamped assembly is baked for a about an hour, the stud is firmly attached to the film and in an otherwise conventional pull test, the film breaks loose from the substrate (or the stud breaks from the epoxy) before the stud breaks from the film.

Method for stud pull test for film formed on semiconductor device

A method and apparatus for monitoring condition of the plasma of a plasma process during processing is disclosed. A spectrum detector (12) detects the intensity of a predetermined wavelength of radiation produced by the plasma process. The output of the spectrum detector is sampled, filtered, and normalized. A parameter calculator (20) calculates a parameter such as velocity or acceleration of the intensity. The calculated parameter is compared to a predetermined threshold. If the parameter exceeds the predetermined threshold, an error condition is indicated.

Method and apparatus for monitoring plasma chamber condition by

The present invention discloses a method for preventing electrostatic discharge damages to an article that is made of an insulating material and stored in a container also made of an insulating material by maintaining a minimum safe distance between the article and the top lid of the container such that a saturation electric field cannot be reached at such safety distance and thus electrostatic discharge does not occur. The present invention novel method can be utilized in carrying any insulating articles but is particularly suitable for carrying a quartz reticle in a polycarbonate pod.

Method for preventing electrostatic discharge damage to an insulating

A photomask arrangement is disclosed to prevent the reticle patterns of a photomask from peeling caused by electrostatic discharge damage. The photomask includes: a substrate; a plurality of metal shielding layers formed on the surface of the substrate to provide the reticle patterns, wherein each two of the metal shielding layers are spaced apart by a clear scribe line; and a plurality of metal lines formed on the clear scribe line to connect the adjacent metal shielding layers, thereby increasing the effective surface area of the reticle patterns.

Photomask arrangement protecting reticle patterns from electrostatic

A method is achieved for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.

Method for reducing surface leakage current on semiconductor intergrated

A structure of a mask for use in a lithography process in a semiconductor fabrication procedure is disclosed. The structure comprising: a mask base being made of transparent material; a plurality of patterns formed on said mask base, said patterns being used for generating an image on a wafer and being made of a conductive opaque material; and a conductive layer formed on said mask base and said plurality of patterns.

Structure of a mask for use in a lithography process of a semiconductor

A method is provided for producing a dummy pattern for an I.C. semiconductor device multi-layer interconnection metallurgy, having a planar global top surface with a dummy pattern for a circuit for use with conductor lines in the circuit pattern. Create a reverse pattern which is a complement of a widened conductor lines in the circuit pattern with openings about the location of the circuit pattern and provide a dummy cross grid pattern. A gridded dummy pattern is generated by creating a dummy grid pattern of the reverse pattern combining it with the negative of the dummy cross grid pattern leaving a cross grid of dummy elements and openings about the location of the circuit pattern. Provide a revised pattern by adding the circuit pattern to the gridded dummy pattern. Take the product of a contact layout pattern multiplied times the sizing operator multiplied times a separation parameter. Then subtract the sized and separated contact layout pattern from the gridded dummy pattern. Then multiply the dummy pattern times a function of sizing operators, and provide a revised contact and circuit pattern by adding the circuit pattern to the sized dummy pattern.

Method of automatic dummy layout generation

An improved method for selecting etch endpoint when dry etching conductive material layers for use in semiconductor device circuits has been created. The more precise endpoint selection procedure produces metallization patterns which are free from residues (resulting from under-etching) and free from sidewall attack and/or pattern degradation (resulting from over-etching). The method avoids costly and time consuming pre-sorting of substrates according to product pattern density.

Dry etch endpoint method

The guard ring is a barrier which prevents contaminates from diffusing through a window opening through insulating layers to adjacent semiconductor devices. The guard ring is formed surrounding a window in the insulation layers over a fuse link or an alignment mark. The guard ring is an annular metal ring that penetrates two or more insulating layers and contacts the substrate.

Contamination guard ring for semiconductor integrated circuit

A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.

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Hsin-Chu, Taiwan

Ying-Chen Chao