Ati Technologies Ulc

Advanced Micro Devices Corporation

Advanced Micro Devices (shanghai) Co., Ltd.

Ati Technologies Inc.

Yinan Jiang

Ahmed M Abdelkhalek

Anthony Asaro

Jeffrey Gongxian Cheng

Andy Sung

Dezhi Ming

Haibo Liu

Guopei Qiao

Zhidong Xu

Xiaowei Wang

Kelly Donald Clark Zytaruk

Dmytro Chenchykov

Shaoyun Liu

Lu Lu

Gongxian Jeffrey Cheng

Shahriar Pezeshgi

Kamraan Nasim

Min Zhang

Hing Pong Chan

LingFei Liu

Bokun Zhang

Vignesh Chander

Zhigang Luo

Guangwen Yang

Kun Xue

Ming-Wei Chien

Sidney D Fortes

Aranyak Mishra

Maria Joo

Xingsheng Wan

ZhenYu Min

WenWen Tang

David Martinez Nieto

Rutao Zhang

Systems and methods are provided related to a scheduler to receive a job request from a virtual function associated with a tenant for execution by at least one processing unit. The scheduler validates the job request in accordance with one or more defined restrictions associated with the tenant and, responsive to successful validation, provides the job request for execution by the processing unit via one or more physical functions associated with the processing unit. In certain embodiments, multi-level enforcement of the defined restrictions are provided via user-mode and kernel-mode drivers associated with the virtual function that are also enabled to validate job requests based on the defined restrictions.

Job limit enforcement for improved multitenant quality of service

A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

Method and apparatus for managing memory

A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for ensuring processing unit hardware state integrity in live migration

A processing system includes physical function circuitry to execute virtual functions and a processing unit configured to operate in a first mode that allows more than one virtual function to execute on the physical function circuitry and a second mode that constrains the physical function circuitry to executing a single virtual function. A first virtual function modifies a state of the processing unit in response to the processing unit being in the second mode. A host driver executing on the processing unit modifies an operating mode indicator to indicate that the processing unit is operating in the first mode or to indicate that the processing unit is operating in the second mode. Microcode executing on the processing unit accesses the operating mode indicator to determine whether the processing unit is operating in the first mode or the second mode.

Modifying device status in single virtual function mode

A processing system selects a reset sequence based on a sideband connected configuration of a plurality of processing units. The processing system identifies whether the plurality of processing units is in the sideband connected configuration, so that the plurality of processing units works together on assigned operations. Based on the identification, the processing system selects and executes one of a plurality of available reset sequences. The processing system is thus able to tailor the executed reset sequence for the configuration of the plurality of processing units, thereby reducing the number of overall system resets and improving processing efficiency.

Processing unit reset based on group configuration

A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a 'time-slice' during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Varying firmware for virtualized device

A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.

Processing unit reset by a virtual function bypassing a host driver

A technique for managing access to a micro engine, the method comprising: determining that a virtual function 'VF') is to be given access to direct communication with a micro engine; in response to the determining, configuring the micro engine to accept direct communication from the VF; monitoring for unpermitted communication; and after a time period has expired, configuring the micro engine to no longer accept direct communication from the VF.

Security for microengine access

A processing system detects excessive requests sent on behalf of a virtual machine executing at the processing system within a predetermined period of time and denies subsequent requests sent on behalf of that virtual machine until after the predetermined period of time has elapsed in order to grant access to resources of the processing system for servicing requests from other virtual machines and to prevent a virtual machine that has been compromised by an attack from overwhelming the processing system with malicious requests. The processing system sets a threshold number of event requests for each type of event request that can occur within a predetermined period of time. If the number of event requests of a certain type exceeds the threshold for that event type, the processing system ignores subsequent event requests of that type until the predetermined period of time has expired.

Event guard for excessive virtual machine requests

A processing system identifies a subset of pages of memory allocated to a source guest virtual machine (VM) running at a first graphics processing unit (GPU) that were modified by the source guest VM and transferring only the subset to a destination guest VM running at a second GPU when performing a live migration from the source guest VM to the destination guest VM. The first GPU maintains a page table of system memory addresses or frame buffer addresses allocated to and accessed by the source guest VM during a session, including an indication of whether the data was modified. Based on the page table information, the processing system identifies and transfers only the modified pages from the source guest VM to the destination guest VM, thereby reducing the time and bandwidth used for migration.

Targeted page migration for guest virtual machine

A technique for recovering from a hang in a virtualized accelerated processing device ('APD') is provided. In the virtualization scheme, different virtual machines are assigned different 'time-slices' in which to use the APD. When a time-slice expires, the APD stops operations for a current VM and starts operations for another VM. To stop operations on the APD, a virtualization scheduler sends a request to idle the APD. The APD responds by completing work and idling. If one or more portions of the APD do not complete this idling process before a timeout expires, then a hang occurs. In response to the hang, the virtualization scheduler informs the hypervisor that a hang has occurred. The hypervisor performs a function level reset on the APD and informs the VM that the hang has occurred. The VM responds by stopping command issue to the APD and re-initializing the APD for the function.

Hang detection for virtualized accelerated processing device

Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.

Multiple application cooperative frame-based GPU scheduling

A processing unit includes a processor core that implements a physical function that supports multiple virtual functions. The processing unit includes a bus interface that supports communication between an external bus and the physical and virtual functions implemented using the processor core. During a reset of the processing unit, power is interrupted to the processor core power to the bus interface is maintained. The bus interface responds to requests for the physical and virtual functions received over the external bus concurrently with the power interruption. The bus interface responds based on state information associated with the virtual function. Power is restored to the processor core in response to the reinitialization of the GPU. The bus interface stops responding to requests for the physical and virtual functions received over the bus interface in response to restoring the power to the processor core and forwards requests received over the external bus from the bus interface to the processor core.

Maintaining visibility of virtual function in bus-alive, core-off state of graphics processing unit

A register protection mechanism for a virtualized accelerated processing device ('APD') is disclosed. The mechanism protects registers of the accelerated processing device designated as physical-function-or-virtual-function registers ('PF-or-VF* registers'), which are single architectural instance registers that are shared among different functions that share the APD in a virtualization scheme whereby each function can maintain a different value in these registers. The protection mechanism for these registers comprises comparing the function associated with the memory address specified by a particular register access request to the &#x201c;currently active&#x201d; function for the APD and disallowing the register access request if a match does not occur.

Growing community of inventors

Markham, Canada

Yinan Jiang