Nan Ya Technology Corporation

Yinan Chen

Ming-Cheng Chang

Jeng-Ping Lin

Hsin-Chuan Tsai

Tse Yao Huang

Tse-Yao Huang

Hsien-Wen Liu

Tieh-Chiang Wu

Tzu-Ching Tsai

Ping Cheng Hsu

Chang-Rong Wu

Kuo-Chien Wu

Hui-Min Mao

Shang-Shu Chung

Jung-Hsing Chien

Li-Han Lu

Chien-Hua Lee

Shih-Chi Hsu

Hsing-Chuan Tsai

Feng-Chuan Lin

Tuz-Ching Tsai

Change-Rong Wu

Hsu Yu-Sheng

Chin-Yuan Hsiao

Shih-chi Hsu

Wen Chi Hsu

Jyh Shorng Horng

A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss.

Semiconductor structure and method of making the same

A method of manufacturing a contact structure to avoid open issue is provided. The method includes the steps of providing a substrate with a contact region, forming an insulating layer to cover the substrate, forming a contact hole in the insulating layer to expose the contact region, conformally depositing a titanium layer on the insulating layer, conformally depositing a titanium nitride layer on the titanium layer, and performing a plasma process on the titanium nitride layer to remove the impurities in the titanium nitride layer.

Method of manufacturing a contact structure to avoid open issue

Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are replaced easily by a polysilicon layer and a BPSG layer.

Method for pre-retaining CB opening

A method and structure for forming deep trenches in a semiconductor substrate is provided. The method comprises: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a pad nitride layer on the pad oxide layer; forming a borophosphosilicate glass layer on the pad nitride layer; forming a borosilicate glass layer on the borophosphosilicate glass layer; and forming deep trenches through the borosilicate glass layer, through the borophosphosilicate glass layer, through the pad nitride, through the pad oxide, and into the semiconductor substrate. The borosilicate glass layer and the borophosphosilicate glass layer function as a composite hard mask in forming the deep trenches. With the borophosphosilicate glass layer, the composite hard mask can be easily removed by dry etch process using hydrogen fluoride vapor after the deep trenches have been formed.

Method and composite hard mask for forming deep trenches in a semiconductor substrate

The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer into the semiconductor substrate, thereby forming a doped region at the periphery of the active area in a channel width direction.

Method for eliminating inverse narrow width effects in the fabrication of DRAM device

This invention relates to a method for self-aligned fabricating an isolation structure of a trench capacitor. The method takes two steps to etch the substrate for forming the shallow trench of the isolation structure, wherein the conductive layer and the collar oxide layer of the trench capacitor remain intact during the etching processes.

Isolation structure for trench capacitors and fabrication method thereof

A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Trench-capacitor DRAM cell having a folded gate conductor

A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.

Method of fabricating contact holes on a semiconductor chip

A two-stage method for making buried strap out-diffusions is disclosed. A substrate having a deep trench is provided. A first conductive layer is deposited at the bottom of the deep trench. A collar oxide is formed on sidewalls of the deep trench. A second conductive layer is deposited within the deep trench atop the first conductive layer. The collar oxide is then etched back to a predetermined depth. A third conductive layer is deposited directly on the second conductive layer. A trench top oxide (TTO) layer is formed on the third conductive layer. A spacer is formed on the sidewalls of the deep trench. A portion of the TTO layer is etched away to form a recess underneath the spacer, which exposing the substrate in the deep trench. Thereafter, a doping process is carried out to form a first diffusion region through the recess, followed by spacer stripping. Finally, a thermal process is performed to out-diffuse dopants of the second conductive layer to the substrate through the third conductive layer, thereby forming a second diffusion region that merges with the first diffusion region.

Method for fabricating buried strap out-diffusions of vertical transistor

A method of forming a gate structure. A substrate having thereon at least one stacked gate is provided. The stacked gate has a gate insulating layer, a polysilicon layer, a silicate layer, and a cap layer. A sacrificial layer is deposited on the substrate, and etched backed to expose the cap layer and an upper portion of the silicate layer. Then, the exposed silicate layer is partially removed to form a recess. The recess is filled with silicon nitride. Finally, a spacer is formed on walls of the stacked gate.

Method of forming a gate structure

The present invention provides a method for making an asymmetric inner structure in a contact or trench having a first sidewall, second sidewall, and a bottom in a semiconductor layer. A conformal dielectric layer is deposited on the interior surface of the contact or trench covering the first sidewall, second sidewall, and the bottom. A title angle ion implantation process is carried out to implant ions into the dielectric layer on the first sidewall and the bottom, but not the dielectric layer on the second sidewall. Thereafter, the doped dielectric layer on the first sidewall and the bottom is selectively etched away and leaving the un-doped dielectric layer on the second sidewall intact.

Method for fabricating asymmetric inner structure in contacts or trenches

The present invention discloses a method of forming a crown capacitor for a DRAM cell. An etching method having different selectivity between the BPSG and silicon oxynitride layer is applied to form a sacrificial structure with a concanovenex sidewall. Using the sacrificial structure as a mold, a high capacitance crown capacitor is obtained.

Method of forming a crown capacitor for a DRAM cell

A method for fabricating a DRAM capacitor is described. First, a semiconductor substrate having a capacitor contact is provided. Next, a first polysilicon layer is formed. Then, an oxide layer and a silicon oxy-nitride layer are sequentially formed over the first polysilicon layer. Next, the silicon oxy-nitride layer, the oxide layer, and the first polysilicon layer are selectively etched to leave a rectangular stack layer. Afterwards, the oxide layer and the first polysilicon layer of the rectangular stack layer are etched from the sidewall direction to leave a double T-shaped stack layer. Then, second polysilicon layer is formed on the upper surface and the sidewall of the double T-shaped stack layer. Next, the second polysilicon layer is selectively removed. The remaining second and first polysilicon layer are used as the bottom electrode. Afterwards, a dielectric layer and an upper electrode are formed on the bottom electrode.

Method for fabricating a DRAM capacitor

The apparatus of the present invention is used to carry substrates processed in an etching process and provides a guiding member to shelter and protect substrates from being dampened by droplets. The apparatus comprises spaced chucks connected to a substrate holder with two arms, respectively. The guiding member is a roof plate disposed under the chucks and abutted against the arms, so that the guiding member can induce the droplets falling from the chucks to flow to the arms. The substrates can be effectively kept dry and clean.

Apparatus for carrying substrates processed in an etching process and

A method of fabricating a stack crown capacitor of a dynamic random access memory (DRAM) cell by using an oxynitride mask is disclosed. First, a dielectric layer and a silicon nitride layer are sequentially deposited over a substrate with an electrical device. Next, forming a contact in the silicon nitride layer and the dielectric layer, and depositing a first polysilicon layer to fill the contact. Next, depositing an oxide layer and an oxynitride layer sequentially, and then defining a bottom electrode pattern for etching the oxynitride layer and the oxide layer. Then, laterally etching the oxide layer, and depositing a second polysilicon layer. Next, etching the second polysilicon layer and the first polysilicon layer by using the oxynitride layer as a mask to form the bottom electrode. Next, removing the oxynitride layer, the oxide layer and partial silicon nitride layer. Finally, forming an interelectrode dielectric layer and a top electrode.

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Taipei, Taiwan

Yinan Chen