Vanguard International Semiconductor Corporation

Yin-Ting Lin

Shao-Chang Huang

Chieh-Yao Chuang

Yung-Chang Chen

Jung-Tsun Chuang

Hung-Wei Chen

Chih-Chuan Ke

Wei-Chung Wu

Han-Pei Liu

Szu-Chi Chen

Sheng-Chih Chuang

Shang-Chuan Pai

Pei-Chun Yu

A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.

Control circuit and operating circuit utilizing the same

A memory unit is provided. The memory unit includes a resistive element, a diode, and a first transistor. The resistive element has a first terminal receiving a bit voltage and a second terminal coupled to a first node. The diode has an anode coupled to the first node and a cathode coupled to a second node. The second node receives a word voltage. The first transistor has a control electrode, a first electrode coupled to the first node, and a second electrode.

Resistive memory and memory cell

Growing community of inventors

Kaohsiung, Taiwan

Yin-Ting Lin