Shanghai Huali Microelectronics Corporation

Shanghai Huali Integrated Circuit Corporation

Yin Long

Hunglin Chen

Qiliang Ni

Kai Wang

Rongwei Fan

Shanshan Chen

Mingsheng Guo

Feijue Liu

MingShen Kuo

Zengyi Yuan

Zhounan Wang

A method for predicting the yield of manufacturing semiconductor devices includes steps of: acquiring defect data of semiconductor devices to be predicted, wherein the semiconductor devices to be predicted include finished semiconductor devices and semi-finished semiconductor devices, and the defect data indicates a defect type and location of at least one defect of the semiconductor devices; inputting the defect data into a pre-trained yield prediction model, wherein the yield prediction model includes a neural network structure and a classification structure, the neural network structure is used to extract defect feature vectors from the defect data, and the classification structure is used to output classification results of qualified or unqualified yield according to the defect feature vectors; and determining, by the yield prediction model, classification results of qualified or unqualified yield of the semiconductor devices.

Method and apparatus for predicting yield of semiconductor devices

The present disclosure discloses a method for detecting a wafer backside defect, comprising: Step 1, providing a signal database comprising signal data corresponding to various different defects, the defects comprising convex defects and concave defects, the signal data reflecting 3D information of the corresponding defect; Step 2, performing backside scanning on a tested wafer by using oblique incident light, and collecting corresponding emitted and scattered light data; and Step 3, comparing the collected emitted and scattered light data with the signal data, and fitting a defect 3D distribution map of the backside of the tested wafer. The present disclosure can test the height or depth of a wafer backside defect and form a 3D distribution map of the wafer backside defect, which is beneficial for analyzing the source of the wafer backside defect and processing it in time, reducing the troubleshooting time and improving the product yield.

Method for detecting wafer backside defect

The present invention provides a method of detecting and measuring the alignment shift of the contacts relative to the gate structures. The method comprises: designing a test model array having different test model regions on the substrate; forming second conductivity type doped well regions, gate structures, and first conductivity type doped active regions in each of the test model regions; forming contacts in each of the test model region; scanning the test model array by an electron-beam inspector to obtain light-dark patterns of the contacts; and detecting and measuring the alignment shift of the contacts relative to the gate structures according to the light-dark patterns of the contacts and the critical dimensions of the transistors in the test model regions.

Method of detecting and measuring contact alignment shift relative to gate structures in a semicondcutor device

The present invention is related to the semiconductor manufacturing field, especially a method for monitoring alignment between contact holes and polycrystalline silicon gate by setting a plurality of equidistant contact holes with same sharp on poly-silicon and residual active area, and then obtain the process alignment profile of the quantized values in the plane in order to have a better control of process quality, thereby have a better control of the quality of the process.

Method for monitoring alignment between contact holes and polycrystalline silicon gate

A method of inspecting misalignment of a polysilicon gate is disclosed, characterized in forming only NMOS devices in P-wells in a test wafer and utilizing an advanced electron beam inspection tool operating with a positive mode to carry out electrical defect inspection. The method can be applied in precisely figuring out the in-plane misalignment of the polysilicon gates of an in-process semiconductor product and identifying a misalignment tendency therebetween across a wafer by verifying all locations of interest thereon, thus providing a methodology for process window optimization and on-line monitoring and contributing to the manufacturing process and yield improvement.

Method of inspecting misalignment of polysilicon gate

A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.

Method of detecting the circular uniformity of the semiconductor circular contact holes

The invention provides a measurement of lateral diffusion of implanted ions in the doped well regions of semiconductor devices comprising: designing a test model having active areas, the P-type and N-type doped well regions of the active areas are separated by STI, and the bottom width of the STI is determined; performing multiple processes on the test model comprising the ion implantation process and the tungsten interconnection process to simulate a semiconductor device structure, wherein during the ion implantation process, in the P-type or N-type doped well regions, only the first procedure of the ion implantation process is performed; scanning the test model, obtaining a light-dark pattern of the tungsten interconnects. The present invention is convenient and accessible and can provide reference to optimize the property of the doped well regions of the semiconductor devices and ensure the yield enhancement.

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Shanghai, China

Yin Long