Taiwan Semiconductor Manufacturing Comp. Ltd.

Yin-Chuan Chuang

Kuan-Ting Liu

Da-Yuan Lee

Ching-Hwanq Su

Chung-Chiang Wu

Hung-Chin Chung

Cheng-Yen Tsai

Wei-Chin Lee

Tai-Wei Hwang

Zhiqiang Wu

Tzer-Min Shen

Chung-Wei Wu

Szu-Wei Huang

Yen-Tien Tung

Zhi-Ren Xiao

Yung-Chien Huang

A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Effective work function tuning via silicide induced interface dipole modulation for metal gates

Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Pre-deposition treatment for FET technology and devices formed thereby

A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.

Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (&#x2014;OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the &#x2014;OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Growing community of inventors

Yunlin, Taiwan

Yin-Chuan Chuang