Ememory Technology Inc.

Amic Technology Corporation

Yin-Chang Chen

Ting-Kuo Yen

Chih-Wei Chen

Po-Hao Huang

Yu-Hsiung Tsai

Wu-Chang Chang

Yang-Chieh Lin

A sense amplifier for a memory includes a transistor, an operational amplifier, and a compensating circuit. The negative input end of the operational amplifier is coupled to the compensating circuit. The positive input end of the operational amplifier is coupled to the drain of the transistor. The output end of the operational amplifier is coupled to the gate of the transistor. The compensating circuit is coupled between the negative input end and the output end of the operational amplifier. The compensating circuit generates a compensating voltage to the negative input end of the operational amplifier according to the voltage of the gate of the transistor.

Sense amplifier with a compensating circuit

A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of the decoding signals is not asserted. The level shift up circuit receives the select signal, outputs the pull-up signal at a first voltage when the select signal is asserted, and outputs the pull-up signal at a second voltage when the select signal is not asserted. The driving circuit has a pull-up transistor for pulling up a control line signal according to the pull-up signal, and a pull-down transistor for pulling down the control line signal according to the pull-up signal.

Control driver for memory and related method

A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring.

Two-phase charge pump circuit without body effect

A memory apparatus includes a plurality of memory units, a sensing circuit and a bias-generating circuit. The plurality of memory units respectively outputs a data current to the sensing circuit, while the sensing circuit further includes a plurality of first transistors, a plurality of second transistors and a plurality of sensing amplifiers. In order to speed up the access time of the memory units, the bias-generating circuit rapidly provides a bias signal to the sensing circuit to turn on the first transistors of the sensing circuit. In the present invention, the sensing circuit uses a common reference voltage to reduce the circuit utilization area of the memory apparatus.

Sensing circuit for memories

Non-volatile memory includes a row driving circuit with shared level shift circuits, so as to minimize the chip area of the non-volatile memory. The row driving circuit includes a plurality of word line driving circuits, a plurality of level shift high circuits, and a plurality of level shift low circuits. The plurality of word line driving circuits share the plurality of level shift high circuits and the plurality of level shift low circuits. Each word line driving circuit includes a plurality of driving units, a level shift high circuit, and a level shift low circuit. The plurality of driving units share the level shift high circuit and the level shift low circuit of the word line driving circuit.

Non-volatile memory having a row driving circuit with shared level shift circuits

A regulator circuit having a voltage output terminal is provided. The regulator circuit includes a current mirror module, a plurality of source followers, and a switch. The current module receives a driving voltage, and has a first current terminal coupled to a driving current and a plurality of second current terminals, so that the driving current is copied to each second current terminal. Furthermore, each of second current terminals is coupled to one of source followers respectively. An output terminal of each source follower is coupled to an input terminal of next source, and the input terminal of the first source follower receives a control voltage. So that the source followers can determine whether the switch conducts the driving voltage to the voltage output terminal or not according to the copied driving current and the control voltage.

Regulator circuit

The voltage source and current source circuits including an amplifier, a first current mirror circuit, a first PMOS transistor, a second current mirror circuit and a NMOS transistor are provided. The amplifier has a positive input terminal and a negative input terminal coupled to the source terminal of the NMOS transistor. The first current mirror circuit is coupled to a reference current and duplicates the reference current to the source terminal of the first PMOS transistor. The first PMOS transistor has a drain terminal, a gate terminal and a source terminal. The drain terminal of the NMOS transistor is coupled to the third current terminal, and the gate terminal of the NMOS transistor is coupled to the source terminal of the first PMOS transistor. The second current mirror circuit duplicates the current from the third current terminal.

Reference voltage source and current source circuits

A boost circuit capable of boosting a reference voltage into an output voltage. The boost circuit includes a main transistor electrically connected to the output voltage, an auxiliary transistor electrically connected to the output voltage, a pre-charge circuit electrically connected to the main transistor and the auxiliary transistor for pre-charging the main transistor and the auxiliary transistor, and a voltage detector electrically connected to the auxiliary transistor and the reference voltage for controlling the auxiliary transistor according to the reference voltage.

Boost circuit with a voltage detector

A semiconductor device includes a negative voltage regulator capable of regulating a negative input voltage and outputting a negative output voltage. The negative voltage regulator has a driver for adjusting the negative output voltage, a first operational amplifier for outputting a driving voltage for controlling a current on a first transistor included in the driver according to a feedback voltage and a reference voltage, a second operational amplifier for outputting a driving voltage for controlling a current of a second transistor, a current source circuit having two triple-well NMOS transistors for providing the driver a current, and a voltage potential divider for generating the feedback voltage by dividing potentials of a voltage source and the negative output voltage and outputting the feedback voltage to the first operational amplifier and the second operational amplifier for adjusting the currents of the first and second transistors thereby regulating the negative output voltage.

Semiconductor device with a negative voltage regulator

A flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers. The flash memory has a row driver for driving a predetermined word line to approach a predetermined voltage level. The row driver has a plurality of word line drivers, and each word line driver has a plurality of driving units and a driving voltage output circuit. The driving voltage output circuit is used for determining operating voltage levels of a plurality of driving voltages according to a plurality of second decoded signals without utilizing a plurality of first decoded signals, and for outputting a predetermined driving voltage to drive the predetermined word line to approach the predetermined voltage level when a driving unit electrically connected to the predetermined word line is turned on for connecting the predetermined word line and the driving voltage output circuit.

Flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers

A regulated charge pump has a negative charge pump for generating a first output voltage according to an oscillation signal, and a regulator. The regulator has a level shift circuit, a differential amplifier for generating a compare signal, and an oscillator for generating the oscillation signal according to the compare signal. The level shift circuit has a plurality serially connected PMOS transistors. A first PMOS transistor has a first source connected to a first reference voltage, and a gate and a drain both connected to an output end of the level shift circuit. A second PMOS has a gate and a drain both connected to an output end of the negative charge pump.

Regulated charge pump

A semiconductor device includes a negative voltage regulator capable of regulating a negative input voltage and outputting a negative output voltage at an output node. The negative voltage regulator has a driver for adjusting the negative output voltage, a first operational amplifier for outputting a driving voltage for controlling a current on a first transistor included in the driver according to a feedback voltage and a reference voltage, a second operational amplifier for outputting a driving voltage for controlling a current of a second transistor, a current source circuit having two triple-well NMOS transistors for providing the driver a current, and a voltage potential divider for generating the feedback voltage by dividing potentials of a voltage source and the negative output voltage and outputting the feedback voltage to the first operational amplifier and the second operational amplifier for adjusting the currents of the first and second transistors thereby regulating the negative output voltage.

A negative voltage switch for use in flash memory. The switch has a control end and two voltage output ends, and includes two inverting units for transferring a positive voltage, two driving units for transferring a negative voltage, and two negative voltage pass-gate transistors for respectively transferring the negative voltage to the voltage outputs. Each inverting unit connects to a driving unit at a corresponding node, and each negative voltage pass-gate transistor connects to one of the nodes. According to a voltage at the control end, the switch turns on one inverting unit to transfer the positive voltage at the corresponding node, and the driving unit connected to the other node turns on to transfer the negative voltage to the corresponding negative voltage pass-gate transistor such that the negative voltage pass-gate transistor stops outputting the negative voltage at the other voltage output.

Negative voltage switch and related flash memory for transferring negative voltage with triple-well transistors

A boosted clock generator has a clock generator for generating a first clock signal, a cross-coupled boost circuit electrically connected to the clock generator for boosting the first clock signal so as to generate a second clock signal, a bootstrap pass gate having an NMOSFET pass gate transistor electrically connected to the cross-coupled boost circuit for passing a higher voltage of the second clock signal, and a level shift circuit electrically connected to the bootstrap pass gate for generating a boosted clock signal according to the higher voltage of the second clock signal.

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Hsin-Chu Hsien, Taiwan

Yin-Chang Chen