Ams International Ag

Yiming Jiang

Robert Kappel

Manfred Lueger

Hesong Xu

Daniele Perenzoni

Daniel Furrer

A time-to-digital converter circuit is disclosed, the time-to-digital converter circuit including a plurality of delay stages connected to form a delay line, a plurality of event counters, an encoder circuit for triggering the delay line, and a binning circuit for associating an event with an event counter from plurality of event counters. The binning circuit selects the event counter based on a signal from the delay line, and wherein the encoder circuit is configured to sequentially trigger a different delay stage of the plurality of delay stages. Also disclosed is a time-of-flight sensor implementing the time-to-digital converter circuit, and an associated apparatus and method.

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Graz, Austria

Yiming Jiang