Taiwan Semiconductor Manufacturing Comp. Ltd.

Cyntec Company

Yimin Huang

Jhy-Jyi Sze

Dun-Nian Yaung

Chen-Jong Wang

Wei-Han Fan

Yu-Hsien Lin

Jen-Cheng Liu

Alexander Kalnitsky

Tung-Ting Wu

Yun Jing Lin

Han-Ting Tsai

Seiji Takahashi

Hsiang-Ku Shen

Ming-Huan Tsai

Chun-Fai Cheng

Pai-Chieh Wang

Feng-Chi Hung

Tung-Heng Hsieh

Chun-Wei Chang

Chun-Feng Nieh

Feng-Jia Shiu

Wei Chuang Wu

Wei-Cheng Hsu

Chin-Chia Kuo

Yuichiro Yamashita

Chung-Hui Chen

Chii-Ming M Wu

Tzu-Chung Wang

Te-Jen Pan

Ching-Chun Wang

Shyh-Fann Ting

Kai-Hsuan Lee

Yen-Ting Chiang

Cheng-Yu Yang

Zhiqiang Wu

Ziwei Fang

Hsueh-Chang Sung

Jeff J Xu

Min Cao

Chun-Tiao Liu

Roger Hsieh

Ming-Jie Huang

Jung-I Lin

Haiting Wang

Shen-Hui Hong

Fung Ka Hing

Inez Fu

King Liao

Sze Jhy-Jyi

Stanely Chen

Wei-Ching Chuang

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a masking layer on a first side of a substrate. A first etching process is performed on the first side of the substrate with the masking layer in place. The masking layer is removed. A second wet etching process is performed on the first side of the substrate after removing the masking layer. The first etching process and the second wet etching process collectively form a plurality of topographical features respectively having a triangular shape in a cross-section.

High performance image sensor

The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.

Semiconductor devices for image sensing

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate. One or more isolation structures are arranged within one or more trenches in the semiconductor substrate. The one or more trenches are disposed along opposing sides of a photo diode region within the semiconductor substrate. The semiconductor substrate includes an undulating exterior having rounded corners arranged laterally between neighboring ones of a plurality of flat surfaces. The rounded corners and the plurality of flat surfaces forming a plurality of triangular shaped protrusions arranged between the one or more isolation structures, as viewed along a cross-sectional view.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device, the method including forming a plurality of photodetectors in a substrate. A device isolation structure is formed within the substrate. The device isolation structure laterally wraps around the plurality of photodetectors. An outer isolation structure is formed within the substrate. The device isolation structure is spaced between sidewalls of the outer isolation structure. The device isolation structure and the outer isolation structure comprise a dielectric material.

Device crack-stop structure to prevent damage due to dicing crack

In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

Semiconductor imaging device having improved dark current performance

An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Semiconductor device including an epitaxy region

The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

Metal reflector grounding for noise reduction in light detector

The present disclosure, in some embodiments, relates to an image sensing integrated chip. The image sensing integrated chip includes a semiconductor substrate having sidewalls defining one or more trenches on opposing sides of a region of the semiconductor substrate. One or more dielectrics are disposed within the one or more trenches. The semiconductor substrate has a plurality of flat surfaces arranged between the one or more trenches. Adjacent ones of the plurality of flat surfaces define a plurality of triangular shaped protrusions and alternative ones of the plurality of flat surfaces are substantially parallel to one another, as viewed along a cross-sectional view.

In some embodiments, the present disclosure relates to an image sensor, including a first photodiode and a second photodiode disposed in a semiconductor substrate. A floating diffusion node is disposed along a frontside of the semiconductor substrate and between the first and second photodiodes. A partial backside deep trench isolation (BDTI) structure is disposed within the semiconductor substrate and between the first and second photodiodes. The partial BDTI extends from a backside of the semiconductor substrate and is spaced from the floating diffusion node. A full BDTI structure extends from the backside of the semiconductor substrate to the frontside of the semiconductor substrate.

Photo diode with dual backside deep trench isolation depth

Various embodiments of the present disclosure are directed towards a capacitor structure comprising a plurality of first conductive layers that are vertically stacked over one another and overlie a substrate. The plurality of first conductive layers respectively contact an adjacent first conductive layer in a first connection region. A plurality of second conductive layers are respectively stacked between adjacent ones of the plurality of first conductive layers. The plurality of second conductive layers respectively contact an adjacent second conductive layer in a second connection region. A dielectric structure separates the plurality of first conductive layers and the plurality of second conductive layers. At least a portion of a lower first conductive layer in the plurality of first conductive layers directly underlies the second connection region.

Metal-insulator-metal capacitor structure to increase capacitance density

In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

A method for forming a semiconductor image sensor includes following operation. A first substrate including a first bottom side and a first top side is provided. A first interconnect structure is disposed under the first bottom side of the first substrate. An insulating structure is formed over the first top side of the first substrate. A conductor penetrating the insulating structure and the first substrate is formed and a first bonding pad is formed in the insulating structure. A second substrate including a second bottom side and a second top side is provided with the second bottom side facing the first top side of the first substrate. A second interconnect structure is disposed under the second bottom side of the second substrate, and a second bonding pad is coupled to the second interconnect structure. The first bonding pad is bonded to the second bonding pad to form a first bonded structure.

Method for forming semiconductor image sensor

Various embodiments of the present disclosure are directed towards a semiconductor structure including a crack-stop structure disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. Photodetectors are disposed within the semiconductor substrate and are laterally spaced within a device region. An interconnect structure is disposed along the front-side surface. The interconnect structure includes a seal ring structure. A crack-stop structure is disposed within the semiconductor substrate and overlies the seal ring structure. The crack-stop structure continuously extends around the device region.

The present disclosure relates to a CMOS image sensor having a doped isolation structure separating a photodiode and a pixel device, and an associated method of formation. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode and a pixel device. The photodiode is arranged within the substrate away from a front-side of the substrate. A pixel device is disposed at the front-side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Comparing to previous image sensor designs, where an upper portion of the photodiode is commonly arranged at a top surface of a front-side of the substrate, now the photodiode is arranged away from the top surface and leaves more room for pixel devices. Thus, a larger pixel device can be arranged in the sensing pixel, and short channel effect and noise level can be improved.

High density image sensor

An image sensor structure and manufacturing method thereof are provided. The image sensor structure includes a substrate with a first surface. A first doped region of a first conductivity type is in the substrate and under the first surface. A second doped region of a second conductivity type is in the substrate and under the first surface. A gate structure is on the first surface of the substrate and overlapping a boundary of the first doped region and the second doped region. The epitaxial structure is on the first surface of the substrate. A method for manufacturing an image sensor structure is also provided.

Image sensor structure and manufacturing method thereof

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Hsinchu, Taiwan

Yimin Huang