Intel Corporation

Yim Pun

Sridhar Lakshmanamurthy

Charles E Narad

Raymond Ng

Lawrence B Huston

Mark B Rosenbluth

Prashant R Chandra

Jeen-Yuan Miin

Wilson Y Liao

Debra Bernstein

Hugh M Wilkinson, Iii

Kin-Yip Liu

David Romano

Larry B Huston

Eric B Selvin

Wing-Cho Fung

Jeen-Yuan Min

Wilson Liao

In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache

Thread-based engine cache partitioning

A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location. The method may additionally include, upon the storing of an end of packet data segment from the packet in its determined second storage location, passing control of the plurality of related data segments to a next processing stage in the processor.

Method and apparatus to assemble data segments into full packets for efficient packet-based classification

In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.

Method and apparatus to communicate flow control information in a duplex network processor system

A method and apparatus for improving network router line rate performance by an improved system for error correction is described. In an embodiment of the present invention, error correction is performed by a hardware-based system within the processing engine of a router's network processor.

Method and apparatus for improving network router line rate performance by an improved system for error checking

A multi-threaded microprocessor with support for packet header splitting during receive packet processing operations and packet header splicing during transmit packet processing operations, as well as optimized recovery of transmit resources, is presented.

Method and apparatus for header splitting/splicing and automating recovery of transmit resources on a per-transmit granularity

A voltage detector for providing an indication of the power supply level. The voltage detector includes a differential amplifier which compares the core voltage supply with the peripheral voltage supply. An output stage receives the determination and outputs a signal indicating whether the core voltage supply is the same as the peripheral power supply or whether the two are different.

Automatic voltage detector control circuitry

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Saratoga, CA, United States of America

Yim Pun