Texas Instruments Corporation

Fujitsu Corporation

Yilun Wang

T-Pinn Koh

Gary Franklin Chard

Douglas Edward Wente

Maxwell G Robertson

Roy Charles McNeil, Jr

Sheng Wu

One example includes network physical link (PHY) switch system. The system includes a multiplexer to output a first of a plurality of data streams that are input to a PHY device in response to a first state of a selection signal. The system also includes a data detector that monitors the first data stream and provides a trigger signal in response to a predetermined condition associated with the first data stream. The system further includes a switching controller that provides the selection signal, and in response to a switching command signal indicating a command to switch from the first data stream to the second data stream, monitors the data detector for the trigger signal and changes the selection signal from the first state to a second state in response to receiving the trigger signal to switch to the second data stream of the plurality of data streams.

Network physical link (PHY) switch system

As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the 'round trip' latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

High resolution, low power design for CPRI/OBSAI latency measurement

A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.

Self-clearing asynchronous interrupt edge detect latching register

A hash function for a MAC bridge filter that improves bridge performance by reducing overflow of the MAC bridge database and which reduces cost of the device by using relatively few hardware resources. A CRC hash function is used to randomize the search string in the MAC bridge filter so that a consistent bridge performance is achieved regardless of where the bridge is used. Using the CRC as a hash function also results in efficient hardware implementation. In addition, the present invention may be generalized to use a CRC-M as hash function for any bridge filter design.

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Dallas, TX, United States of America

Yilun Wang