Apple Inc.

Yildiz Sinangil

Mohamed Hassan Abu-Rahma

Ajay Bhatia

Anthony Ghannoum

Paolo Di Febbo

Chaminda Nalaka Vidanagamachchi

Jaroslav Raszka

Shahzad Nazar

Aravind Kandala

Bharan Giridhar

Jelam K Parekh

Mohammad Ghasemzadeh

Mayur V Joshi

A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of the global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit.

Performing multiple bit computation and convolution in memory

An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

Acceleration of in-memory-compute arrays

A system and method for efficiently managing switching power of bit lines. In various embodiments, a first bit line in a memory array is pre-charged in multiple discrete steps, rather than in one continuous step. For a read operation that completed and read a logic low level from a first storage node, the first bit line is pre-charged from a ground reference level to a first power supply voltage. Similarly, a second bit line corresponding to a second storage node storing an inverse voltage level of the first storage node is pre-charged from a larger second power supply voltage to the smaller first power supply voltage. When the first time interval has elapsed, the first and second bit lines are pre-charged from the first power supply voltage to the second power supply voltage during a second time interval. Discrete steps are also used for pre-charging after write operations.

Technique to lower switching power of bit-lines by adiabatic charging of SRAM memories

Systems, apparatuses, and methods for reducing leakage current for a memory array. In various embodiments, techniques are implemented for generating a supply voltage for a memory array which tracks the data retention voltage of the memory array. In one embodiment, multiple diodes are implemented in parallel between a supply voltage and the memory array. The diodes have different sizes and different voltage drops, and the diode which will cause the voltage to drop closest to without going below the data retention voltage is selected for routing the supply voltage to the memory array. Since the data retention voltage for the memory array varies over temperature, the temperature of the system is monitored. Based on changes in the temperature, the system changes which diode is in the circuit path for supplying power to the memory array so as to reduce leakage current for the memory array.

Adaptive diode sizing techniques for reducing memory power leakage

In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage distribution circuit may connect a word line driver circuit to a bit-cell voltage circuit such that an operating voltage is received at a bit-cell circuit before a word line signal form the word line driver circuit is received at the bit-cell circuit, where the operating voltage is provided by the bit-cell voltage circuit. The method may further include the bit-cell circuit providing the operating voltage along a bit line based on a data stored at the bit-cell circuit and based on the word line signal. In some embodiments, a static noise margin of one or more portions of the bit-cell circuit may be improved. Additionally, in some cases, a wakeup time of the bit-cell circuit may be ignored, resulting in a faster read operation.

Bit-cell voltage distribution system

In some embodiments, a system includes a bit-cell circuit and a body voltage control circuit. During a sleep mode, the bit-cell circuit receives, via a source node of a transistor, a retention voltage. During an active mode, the bit-cell receives, via the source node, an operating voltage. The body voltage control circuit includes a first transistor that connects a body node of the transistor of the bit-cell circuit to the source node such that during the sleep mode, the body node receives the retention voltage. The body voltage control circuit further includes a second transistor that connects the body node to a voltage source such that during the active mode, the body node receives the operating voltage.

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Sunnyvale, CA, United States of America

Yildiz Sinangil