Via Technologies, Inc.

Yijung Su

Yang (Jeff) Jiao

John Wakefield Brothers

Fred Liao

Yiping Chen

Mark Zheng

Hsilin Huang

Qunfeng (Fred) Liao

Kuoyin Weng

Embodiments of the present disclosure are directed to graphics processing systems, comprising: a plurality of execution units, wherein one of the execution units is configurable to process a thread corresponding to a rendering context, wherein the rendering context comprises a plurality of constants with a priority level; a constant buffer configurable to store the constants of the rendering context into a plurality of slot in a physical storage space; and an execution unit control unit configurable to assign the thread to one of the execution units; a constant buffer control unit providing a translation table for the rendering context to map the corresponding constants into the slots of the physical storage space. Comparable methods are also disclosed.

Constant buffering for a computational core of a programmable graphics processing unit

The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked.

System and method for dynamically load balancing multiple shader stages in a shared pool of processing units

Embodiments of systems and methods for managing a constant buffer with rendering context specific data in multithreaded parallel computational GPU core are disclosed. Briefly described, one method embodiment, among others, comprises responsive to a first shader operation, receiving at a constant buffer a first group of constants corresponding to a first rendering context, and responsive to a second shader operation, receiving at the constant buffer a second group of constants corresponding to a second context without flushing the first group.

Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.

Systems and methods for managing texture descriptors in a shared texture engine

Provided is a system for managing multiple contexts in a decentralized graphics processing unit. The system includes multiple control units that can include a context buffer, a context processor, and a context scheduler. Also included is logic to receive multiple contexts, logic to identify at least one of the contexts, and logic to facilitate communication among the control units.

Managing multiple contexts in a decentralized graphics processing unit

Provided are methods for managing texture data in Graphics Processing Units (GPUs). The methods include receiving, into an arbiter, a preload request configured to request processing of texture data in advance of shader processing and receiving, into the arbiter, a dependent read request configured to request processing of texture data after shader processing. The methods also include receiving, into the arbiter, a capacity signal from a texture buffer and determining, utilizing the virtual buffer capacity signal, a selected request corresponding which of the preload request and the dependent read request is granted. The methods further include processing, in a texture processor, texture data corresponding to the selected request.

Systems and methods for managing texture data in a computer

Method and system for controlling the dynamic latency of an arithmetic logic unit (ALU). In one embodiment, the identification of the destination operand of an instruction is stored in a temporary register ID/thread control ID pair pipeline if the destination operand is a temporary register. Furthermore, each source operand of an instruction is checked against the identifications stored in a group of temporary register ID/thread control ID pipelines. If a source operand is matched to an identification stored in the temporary register ID/thread control ID pipelines, the ALU does not execute the instruction until the matched identification is no longer matched in the pipelines.

Growing community of inventors

Alviso, CA, United States of America

Yijung Su