Exar Corporation

Raytheon Company

Yihe Huang

Charles L Vinn

The present invention is directed to a decoder circuit that can be operated at higher frequencies of a RLL clock. RLL data input from a disk drive is shifted through a first stage of the decoder circuit by the standard RLL clock. The RLL data is shifted from the first stage through a second stage of the decoder circuit by a modified RLL' clock that operates at a lower frequency than the RLL clock. In a preferred embodiment, RLL' clock operates at one-third the frequency of the RLL clock. The decoding step is accomplished within the period of one clock cycle of the slower RLL' clock, which affords the decoder circuit of the present invention a sufficient amount of time to decode the RLL data from the disk drive into NRZ data for the host. Since RLL' clock used in the decoding step is slower, the RLL clock used to generate RLL' clock and to clock data into the decoder circuit from the disk drive can be operated at a higher frequency than currently possible. This improvement in the speed of the RLL clock provides an improvement in the throughput of data from disk drive to host.

RLL to NRZ decoder circuit in disk drive read/write channel

A simple structure for switching between two clock signals to produce an output without a glitch or short pulse. The invention is basically a three-input multiplexer controlled by a modified two-bit state machine. The state machine includes flip-flop memories which are driven by the two different clocks, as opposed to using a single clock as in a traditional state machine. The state machine output is used to control the three-input multiplexer, selecting between the first clock, the second clock and an intermediate high level signal during transition. The intermediate high level signal bridges the gap between pulses, eliminating any short glitches.

Clock generator using a state machine to switch between two offset clocks

An encoder circuit in the read/write channel of a disk drive encodes NRZ data from a host computer into RLL data to be stored in the disk drive even at high frequencies of the RLL clock. Serial NRZ input data is first converted into two parallel NRZ data signals. The second NRZ signal is delayed by one clock cycle with respect to the first NRZ signal. A clock derived from the NRZ clock signal clocks the parallel NRZ signals through a first stage of flip-flops. An RLL clock signal then drives the parallel data signals through the remaining stages of flip-flops into a block of combinational encoding logic, where the NRZ data signals are converted into RLL data output to be stored on the disk surface. By splitting the serial NRZ input into two parallel signals and clocking the signals with a clock derived from the NRZ clock, the NRZ data is made valid for a longer period of time, making the encoder circuit less susceptible to the problem of clock drift which might cause asynchronous circuit operation.

NRZ to RLL encoder circuit in disk drive read/write channel

A simple, reliable, divide by 1.5 clock generator is provided. This is done by using a divide by 3 circuit with three gates. The first two gates are clocked by the RLL clock, and the third gate is clocked by the inverse of the RLL clock. The output of the first gate is combined with the RLL clock to provide an output pulse. Another output is produced when the output of the third gate is combined with the inverse of the RLL clock. The combination of these two outputs thus produces a divide by 1.5 clock with a precisely placed rising edge. The output clock is not symmetrical, but the rising edge (or the falling edge on its inverse) is precisely placed at the 1.5 frequency.

High speed divide by 1.5 clock generator

A circuit for increasing the slew rate of linear amplifier circuits. The circuit comprises two NPN and PNP transistor pairs arranged so that when the voltage level difference between the amplifier output and input voltage exceeds the base to emitter voltage of such transistors, the circuit is activated. The circuit provides a current proportional to such voltage difference in order to speed up the charging or discharging of the slew rate determining capacitance.

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Palo Alto, CA, United States of America

Yihe Huang