Taiwan Semiconductor Manufacturing Comp. Ltd.

Yih-Yuh Doong

Lien Jung Hung

Keh-Jeng Chang

Yuh-Jier Mii

Sally Liu

Victor Chih Yuan Chang

Ru-Gun Liu

Chih-Ming Lai

Tsong-Hua Ou

Ying-Chou Cheng

Yao-Ching Ku

Cliff Hou

Min-Hong Wu

Yi-Kan Cheng

Jye-Yen Cheng

Chien-Jung Wang

Hsiao-Shu Chao

Chien-Chang Lee

Tseng Chin Lo

Chia-Chi Lin

Sung Chun Hsieh

Chih-Chieh Shao

Ching-Hsiang Hsu Charles

Tsu-bin Shen

Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.

Accurate capacitance measurement for ultra large scale integrated circuits

An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.

Method for shape and timing equivalent dimension extraction

An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.

Test pad design for reducing the effect of contact resistances

A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.

Electrical parameter extraction for integrated circuit design

This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUT) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.

Versatile semiconductor test structure array

A test structure for detecting defects in a semiconductor wafer and a method for using such test structure are provided. The test structure includes conduction units arranged in an array and test pads connecting to the conduction units. A conduction unit includes closely spaced or intermeshed conduction paths. The test pads are divided into X and Y groups. A pair of test pads X(i), X(i&plus;1) are set to high voltage, a pair of test pads Y(j), Y(j&plus;1) are set to low voltage, and the other test pads are floated. The current I(i, j) flowing from test pad pairs X to Y is measured. If current I(i, j) is a local minimum, then conduction unit (i, j) has a short circuit defect.

Method and device for addressable failure site test structure

Microanalysis of small areas on insulating substrates can be a problem because of charge and thermal buildup. One solution has been to coat the underside of the area with a layer of thermally and electrically conductive material. This becomes very difficult to do when there is no clear access to the surface in question. The present invention solves this problem by forming two cavities, on opposite sides of the area that is to be microanalyzed, that extend downwards into the substrate at an angle to its surface so that they intersect directly below the microanalysis area. The result is a cavity that is bridged by a beam having a triangular cross-section. Part of said beam is then selectively removed, resulting in a cantilever that extends out over the cavity with the microanalysis area located near its free end. Coating of the cantilever's underside is achieved by using a focused ion beam to first deposit the layer in question on the two lower sloping surfaces of the cavity. Then, as a result of sputtering by the ion beam itself, some of this material is ejected and redeposits on the underside of the beam.

Structure for FIB based microanalysis and method for manufacturing it

A semiconductor memory device comprising a test structure is disclosed. The semiconductor device includes a plurality of memory cells, word lines, bit lines, and test pads; the word lines including a first set and a second set of word lines, connected to a first and second word line test pad, respectively; the bit lines including a first set and a second set of bit lines, connected to a first and second bit line test pad, respectively. The first set of word lines and the first set of bit lines access a first set of memory cells, the first set of word lines and the second set of bit lines access a second set of memory cells, the second set of word lines and the first set of bit lines access a third set of memory cells, and the second set of word lines and the second set of bit lines access a fourth set of memory cells. By applying a predetermined set of test signals to the first and second word line test pads, and the first and second bit line test pads, the disturbance or interference among the first, second, third, and fourth set of memory cells can be measured.

Semiconductor device comprising a test structure

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Hsin-Chu, Taiwan

Yih-Yuh Doong