Vishay General Semiconductor, Inc.

General Semiconductor of Taiwan, Ltd.

Yih-Yin Lin

Chih-Wei Hsu

Florin Udrea

Chih-Ping Peng

Wan-Lan Chiang

Shih-Kuan Chen

Ming-Tai Chiang

Max Sk Chen

Tung-Chieh Lin

Christopher Michael Knowles

Richard Sean O'Rourke

William John Nelson

Hung-Ping Tsai

Pai-Li Lin

A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.

Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current

A semiconductor device includes a substrate having first and second sides and a first active layer disposed over the first side of the substrate. A second active layer is disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. At least one trench extends through the first and second active layers and the two-dimensional electron gas layer and into the substrate. A conductive material lines the trench. A first electrode is disposed on the second active layer and a second electrode is disposed on the second side of the substrate.

Gallium nitride power semiconductor device having a vertical structure

A semiconductor device includes a first active layer disposed over a substrate. The second active layer is disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. The first electrode establishes a Schottky junction with the second active layer. The first electrode includes a first electrode pad and a first series of fingers in electrical contact with the first electrode pad. The second electrode establishes an ohmic junction with the first active layer. The second electrode includes a second electrode pad and a second series of fingers in electrical contact with the second electrode pad. The first and second series of electrode fingers form an interdigitated pattern. The first electrode pad is located over the first and second series of electrode fingers.

GaN-based schottky diode having large bond pads and reduced contact resistance

Zener diode haviing a polysilicon layer for improved reverse surge capability and decreased leakage current

A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.

GaN-based Schottky diode having dual metal, partially recessed electrode

A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.

GaN-based Schottky diode having partially recessed anode

A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.

Trench DMOS device with improved termination structure for high voltage applications

A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate and a second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover a portion of the termination structure oxide layer.

Trench MOS device with improved termination structure for high voltage applications

A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

Schottky rectifier

A wafer-level process for fabricating a plurality of passivated semiconductor devices comprising the steps of providing a semiconductor wafer on that at least one p-n junction is formed, Cutting a plurality of grooves in said wafer to expose said at least one p-n junction, wherein each of said grooves extends partly through the wafer and has a depth that is enough to expose said at least one p-n junction, applying a passivating material into said grooves and curing the material. The grooves can be formed by using a disc saw having a blade, by performing a sandblasting operation within a controlled operation time, or by performing a photolithographically chemical etching process. The passivating material is either screen-printed or pin-dispensed into the grooves. A dicing operation can be subsequently proceeded to divide the wafer into individual chips for subsequent fabrication into completed semiconductor devices.

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Taipei, Taiwan

Yih-Yin Lin