Taiwan Semiconductor Manufacturing Comp. Ltd.

Yih Wang

Chia-En Huang

Meng-Sheng Chang

Yi-Ching Liu

Perng-Fei Yuh

Sai-Hooi Yeong

Jui-Che Tsai

Ku-Feng Lin

Yao-Jen Yang

Hiroki Noguchi

Chia-en Huang

Yu-Ming Lin

Hidehiro Fujiwara

Shao-Yu Chou

Tung-Cheng Chang

Yi-Hsun Chiu

Han-Jong Chia

Chieh Lee

Shih-Lien Linus Lu

Bo-Feng Young

Fu-An Wu

Gu-Huan Li

Chun-Ying Lee

Yen-Huei Chen

Meng-Han Lin

Jonathan Tsung-Yung Chang

Tzu-hsien Yang

Carlos H Diaz

Zhiqiang Wu

Yu-Der Chih

Mahmut Sinangil

Chia-Ta Yu

Martin Liu

Yoshitaka Yamauchi

Chien-Ying Chen

Gaurav Gupta

Kerem Akarvardar

Wen-Chang Cheng

Wan-Hsueh Cheng

Chen-Hua Douglas Yu

Kuan-Lun Cheng

Ching-Wei Tsai

Chuei-Tang Wang

Tzu-Chiang Chen

Hung-Li Chiang

Chung-Hao Tsai

Chia-Cheng Chen

Yu-Xuan Huang

Chansyun David Yang

Chung-Wei Wu

Keh-Jeng Chang

Chenchen Jacob Wang

Yen-Ting Lin

Peng-Chun Liou

Shao-Ting Wu

Qing Dong

Yu-Wei Lin

Philex Ming-yan Fan

Shao-yu Chou

Philex Ming-Yan Fan

Hung-Jen Liao

Jen-Yuan Chang

Yu-Hao Hsu

Haruki Mori

Yu-Fan Lin

Pei-Chun Liao

Yu-Kai Chang

Nail Etkin Can Akkaya

Rose Tseng

Chang Jen-Yuan

Jimmy Lee

A memory device includes a programming gate-strip, a read gate-strip, and an array of one-bit memory cells. Each one-bit memory cell includes an anti-fuse structure, a transistor, a terminal conductor, a group of programming conducting lines, and a bit connector. The anti-fuse structure has a dielectric layer overlying a semiconductor region in an active zone at an intersection of the programming gate-strip and the active zone. The transistor has a channel region in the active zone at an intersection of the read gate-strip and the active zone. The terminal conductor overlies a terminal region of the transistor in the active zone. The group of programming conducting lines is conductively connected to the programming gate-strip through a group of one or more gate via-connectors. The bit connector is conductively connected to the terminal conductor through one or more terminal via-connectors.

Memory device with improved anti-fuse read current

A memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. The first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.

Memory devices with dual-side access circuits and methods for operating the same

A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

One-time-programmable memory device including an antifuse structure and methods of forming the same

Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.

Switches to reduce routing rails of memory system

The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

High-voltage nano-sheet transistor

A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.

DRAM computation circuit and method

Magnetic random access memory (MRAM) cells are provided. MRAM cell includes a plurality of stacked magnetic tunnel junction (MTJ) devices coupled in serial and coupled between a bit line and a source line. The stacked MTJ devices have different sizes. Each of the stacked MTJ devices includes a free layer, a pinned layer and a barrier layer between the free layer and the pinned layer. The free layers of two adjacent stacked MTJ devices are in direct contact with each other.

MRAM cell and MRAM

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

Memory circuits

A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

Memory devices and methods of manufacturing thereof

Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Non-volatile static random access memory (NVSRAM) with multiple magnetic tunnel junction cells

Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Memory including metal rails with balanced loading

One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Using embedded switches for reducing capacitive loading on a memory system

A method (of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second S/D terminal; and wherein the first source/drain voltage is lower than the gate voltage.

Method of writing to or erasing multi-bit memory storage device

A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Memory device and operating method of the same

A memory device includes first nanostructures stacked on top of one another; first gate stacks, where two adjacent ones of the first gate stacks wrap around a corresponding first nanostructure; second nanostructures stacked on top of one another; second gate stacks, where two adjacent ones of the second gate stacks wrap around a corresponding second nanostructure; a first drain/source feature electrically coupled to a first end of the first nanostructures; a second drain/source feature electrically coupled to both of a second end of the first nanostructures and a first end of the second nanostructures; and a third drain/source feature electrically coupled to a second end of the second nanostructures. At least one of the plurality of first gate stacks is in direct contact with at least one of the first drain/source feature or the second drain/source feature.

Growing community of inventors

Hsinchu, Taiwan

Yih Wang