Integrated Device Technology, Inc.

Simpod, Inc,

Yiftach Tzori

Avigdor Willenz

A digital logic simulation/emulation system (,) operates in an engaged operating mode in which a digital-logic simulation process (,) transmits stimulation-control data to a hardware pod (,) for controlling stimulation of a digital logic circuit. In response to the stimulation-control data, the hardware pod (,) performs a stimulation-response cycle, and then sends response data from the digital logic circuit to the simulation process (,). The simulation process (,) and the hardware pod (,) may also operate in a disengaged operating mode in which each operates independently of the other without exchanging stimulation-control data or response data. Operation of the system (,) in the disengaged mode commences if a disengagement event occurs in the hardware pod (,). Operation of the system (,) in the disengaged mode terminates if the simulation process (,) sends stimulation-control data to the hardware pod (,), or if the hardware pod (,) sends response data to the simulation process (,).

Concurrent hardware-software co-simulation

A structure and a method provide data integrity for a multiprocessor system having a cache memory and a snoop tag cache. In one embodiment, the snoop tag cache copies the tags of a primary cache. Whenever a write operation occurs, the snoop tag cache is accessed to determine if the accessed tag matches a predetermined portion of the address of the memory location on which the write operation is performed. If so, a signal is sent to the CPU associated with the primary cache so that the corresponding entries in the primary cache and the snoop tag cache can be invalidated.

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Sunnyvale, CA, United States of America

Yiftach Tzori