International Business Machines Corporation

Qualcomm Incorporated

Globalfoundries Inc.

Yiftach Benjamini

Bartholomew Blaner

Etai Adar

Lakshminarayana Baba Arimilli

Michael Bar-Joshua

Michael Grubman

William John Starke

Jeffrey A Stuecheli

Amit Gil

Shaul Yohai Yifrach

Alexander Mesh

Eyal Gonen

Pavel Granovsky

Daniel Mark Dreps

Yang Liu

Michael Steven Siegel

Richard Dominic Wietfeldt

Lalan Jee Mishra

Kai Yang

John David Irish

Kenneth Michael Valk

Lior Amarilio

David John Krolak

Curtis Carl Wollbrink

Sharon Graif

Cheng Song

Adrian Stephen Butter

Lonny Lambrecht

Yaakov Gendel

Oren Lev

Tomer Z Metz

Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

Sideband signaling in universal serial bus (USB) type-C communication links

Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

Time synchronization for clocks separated by a communication link

Systems and methods for scrambling data-port audio in SOUNDWIRE&#x2122; systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Scrambling data-port audio in SOUNDWIRE systems

Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Updating cache using two bloom filters

Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

Managing lowest point of coherency (LPC) memory using a service layer adapter

Managing execution of computer operations by determining that a computer resource targeted by a command's first operation is available, in a candidate processing record in a processing records schedule, to receive an instruction to perform the first operation, determining that a computer resource targeted by the command's second operation is available, in a processing record in the schedule at a processing offset relative to the candidate record, to receive an instruction to perform the second operation, the processing offset being an expected processing latency associated with the command, scheduling the computer resource targeted by the first operation to receive the instruction to perform the first operation when processing the candidate record in the schedule, and scheduling the computer resource targeted by the second operation to receive the instruction to perform the second operation when processing the processing record in the schedule at the processing offset relative to the candidate record.

Managing execution of computer operations with non-competing computer resource requirements

Various examples of techniques for identifying a corrupt data lane and using a spare data lane are described herein. Some examples include a system of coordinating spare lane usage between link partners. One such example comprises analyzing data from a link partner to identify a corrupt lane, and communicating the corrupt lane to the link partner, wherein the communication does not require sideband communication channel. In some embodiments, communicating the corrupt lane to the link partner comprises identifying a transmit lane corresponding to the corrupt lane, transmitting a set of data intended for a corresponding transmit lane using a spare data lane, and transmitting bad data to the link partner using the corresponding transmit lane.

Coordination of spare lane usage between link partners

A computer-implemented method includes identifying a current packet data transmission credit value assigned to a packet data transmitter. The method includes identifying a value change in the current packet data transmission credit value. The baseline packet transmission credit value is for the packet data transmitter. The method is responsive to the change being a decrease by increasing a transmission opportunity weight for the packet data transmitter. The method is responsive to the change being an increase by decreasing the transmission opportunity weight for the packet data transmitter. The method includes passing to the packet data transmitter a parameter. The parameter directing the packet data transmitter to transmit packet data via data transmission circuitry during a scheduled transmission opportunity. The extent of the parameter is proportional to the transmission opportunity weight.

Controlling packet data transmissions via data transmission media

A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.

Pre-transmission data reordering for a serial interface

Direct memory access between an accelerator and a processor using a coherency adapter including receiving, by the adapter from the accelerator, a request to initiate a DMA transfer; providing, by the adapter, a translation tag ('XTAG') to the accelerator; receiving, by the adapter from the accelerator, a DMA instruction comprising the XTAG; generating, by the adapter, a DMA instruction comprising a real address based on the XTAG; and sending, by the adapter, the generated DMA instruction comprising the real address to a communications bus.

Direct memory access between an accelerator and a processor using a coherency adapter

A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.

Processing commands in a directory-based computer memory management system

Growing community of inventors

Givat Ela, Israel

Yiftach Benjamini