Applied Materials, Inc.

Lam Research Corporation

Yifeng Zhou

Srinivas D Nemani

Ellie Y Yieh

Khoi Doan

Dmitry Lubomirsky

Qian Fu

Gowri Kamarthy

Jeremiah T P Pender

Siyi Li

Thorsten B Lill

Harmeet Singh

Meihua Shen

Nicolas J Bright

Michael D Armacost

Baosuo Zhou

Gerardo Delgadino

Yoshie Kimura

Monica Titus

Jeremiah T Pender

John Hoang

Terry Leung

Tae Won Kim

Ming-Shu Kuo

Ratndeep Srivastava

Jamie Saephan

Chang-Lin (Peter) Hsieh

Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include one or more patterned features separated by exposed regions of the substrate. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor. Forming the plasma of the silicon-containing precursor and the hydrogen-containing precursor may be performed at a plasma power of less than or about 1,000 W. The methods may include depositing a silicon-containing material on the one or more patterned features along the substrate. The silicon-containing material may be deposited on the patterned features at a rate of at least 2:1 relative to deposition on the exposed regions of the substrate.

Selective silicon deposition

Described herein is a method for etching a sample. The method includes performing a plasma etch pulse. The plasma etch pulse is performed by directing a gas flow comprising silicon tetrachloride (SiCl) and a diluent towards the sample. While directing the gas flow, a bias power is applied to achieve a bias state for a first time period. Then, a source power is applied to achieve a source state for a second time period, and then no bias power and no source power is applied to achieve a recovery state for a third time period. The plasma etch pulse is repeated until a target amount of the sample is etched.

Pulsed etch process

A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber

A method for forming via holes in an etch layer disposed below a patterned organic mask with a plurality of patterned via holes is provided. The patterned organic mask is treated by flowing a treatment gas comprising H. A plasma is formed from the treatment gas. The patterned via holes are rounded to form patterned rounded via holes by exposing the patterned via holes to the plasma. The flow of the treatment gas is stopped. The plurality of patterned rounded via holes are transferred into the etch layer.

Method for providing vias

Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Trenches are formed in the exposed portions of the low-k dielectric layer. A plurality of process cycles is performed to remove the photoresist layer. Each process cycle includes forming a silicon source layer on surfaces of the trenches of the low-k dielectric layer, and exposing the photoresist layer to an oxygen source to form an Si&#x2014;O-containing layer on the surfaces of the trenches of the low-k dielectric layer and to remove at least a portion of the photoresist layer.

Method of removing a photoresist from a low-k dielectric film

Methods of multiple patterning of low-k dielectric films are described. For example, a method includes forming and patterning a first mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. A second mask layer is formed and patterned above the first mask layer. A pattern of the second mask layer is transferred at least partially into the low-k dielectric layer by modifying first exposed portions of the low-k dielectric layer with a first plasma process and removing the modified portions of the low-k dielectric layer. Subsequently, a pattern of the first mask layer is transferred at least partially into the low-k dielectric layer by modifying second exposed portions of the low-k dielectric layer with a second plasma process and removing the modified portions of the low-k dielectric layer.

Method of multiple patterning of a low-K dielectric film

Post etch treatments (PETs) of low-k dielectric films are described. For example, a method of patterning a low-k dielectric film includes etching a low-k dielectric layer disposed above a substrate with a first plasma process. The etching involves forming a fluorocarbon polymer on the low-k dielectric layer. The low-k dielectric layer is surface-conditioned with a second plasma process. The surface-conditioning removes the fluorocarbon polymer and forms an Si&#x2014;O-containing protecting layer on the low-k dielectric layer. The Si&#x2014;O-containing protecting layer is removed with a third plasma process.

Post etch treatment (PET) of a low-K dielectric film

Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.

Method of patterning a low-K dielectric film

Methods of patterning low-k dielectric films are described.

A significantly improved low-k dielectric patterning method is described herein using plasma comprising an oxygen radical source and a silicon source to remove the photo-resist layer.

Method of patterning a low-k dielectric film

A substrate comprising a resist layer overlying a dielectric feature, is processed in a substrate processing chamber comprising an antenna, and first and second process electrodes. A process gas comprising COis introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage to the antenna, and by applying to the electrodes, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz. The ratio of the power level of the first bias voltage to the second bias voltage is sufficient to obtain an edge facet height of the underlying dielectric feature that is at least about 10% of the height of the dielectric feature.

Plasma for resist removal and facet control of underlying features

A plasma etch process includes a plasma etch step performed with a photoresist mask on a workpiece using a polymerizing etch process gas that produces in the plasma polymerizing species which accumulate as a protective polymer layer on the surface of said photoresist mask during the etch step, the process including the following steps performed in the same chamber after the etch step and prior to removing the photoresist mask:

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Fremont, CA, United States of America

Yifeng Zhou