Broadcom Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Yifei Zhang

Mark Jon Winter

Myron Buer

Carl A Monzel

Saket Gupta

Carl Monzel

A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.

Write assist circuit for lowering a memory supply voltage and coupling a memory bit line

Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in each array cell or bitcell. For example, one or more memory cells may be converted to provide passive write assist to a plurality of other memory cells. As another example, each memory cell may independently implement passive write assist using one or more high resistive contacts to couple to the array power supply, resulting in the array voltage level being changed by different amounts in different memory cells according to cell variations.

Passive SRAM write assist

A device for monitoring process variations across memory bitcells includes a bitcell inverter that provides an output voltage to be used for identifying skewed corners of the memory bitcells. A first comparator compares the output voltage with a first reference voltage, and a second comparator compares the output voltage with a second reference voltage. The first and the second comparators generate a corner code based on comparison results.

All voltage, temperature and process monitor circuit for memories

Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.

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Edina, MN, United States of America

Yifei Zhang