University of Florida Research Foundation, Incorporated

Washington University

Yier Jin

Shaojie Zhang

Xuan Zhang

Huifeng Zhu

James Geist

Jason Liam Portillo

Yichen Jiang

Travis Meade

Xiaolong Guo

Embodiments provide for predicting rowhammer attack vulnerability of one or more memory cells of a direct random access memory (DRAM) chip, the DRAM chip including a plurality of memory cells. An example method, determines, for each memory cell of a subset of memory cells of the plurality of memory cells, a leakage time t, a resistance of intrinsic leakage Rbased at least in part on the leakage time t, an activation time of an adjacent aggressor row to flip a bit in the memory cell, a resistance of coupling leaking Rbased at least in part on the activation time, and a toggling count. The method identifies, based at least in part on one or more of the R, R, or toggling count, whether the direct random memory access (DRAM) chip is vulnerable to a rowhammer attack.

Fast and efficient system and method for detecting and predicting rowhammer attacks

Embodiments herein provide for reverse engineering of integrated circuits (ICs) for design verification. In example embodiments, an apparatus receives a gate-level netlist for an integrated circuit (IC), generates a list of equivalence classes related to signals included in the gate-level netlist, determines control signals of the gate-level netlist based at least in part on the list of equivalence classes, determines a logic flow of a finite state transducer (FST) based at least in part on the control signals, and generates register transfer level (RTL) source code for the IC based on the FST.

System and method for fast and accurate netlist to RTL reverse engineering

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Gainesville, FL, United States of America

Yier Jin