Cisco Technology, Inc.

Tandem Computers Incorporated

Yie-Fong Dan

Sonny N Tran

Bruce Alexander Wilford

Raymond Ng

Duc Manh Hoang

David Anthony Hughes

Tong Liu

Pawel Piotr Sowinski

Kenneth K Chan

Geoffrey I Iswandhi

William Beebee

Martin W Sanner

Chad Mikkelson

Steven J Faulkner

Wing M Chan

James E Korpi

Rudy Klecka

Jay A Zwagerman

Shi-Jie Wen

Robert O'Grady

Edmund Au

Steven G Silverman

Yanyan Cui

Zubair Hussain

David L Bernick

Steven Man Pak Yip

James E Smith

Michael T Chin

A method that determines the system impact of single event upset (SEU) and a single event upset (SEU) wrapper that controls a SEU controller is disclosed. The method injects faults into a component (e.g. FPGA, ASIC) of an operational system that is carrying live traffic and monitors the system's response to the faults to determine the impact of SEU on the system. The SEU wrapper sends the SEU controller a pattern scheme that includes information indicating when, where, how often, and/or how long to inject bursts of one or more faults into memory of the component of the system. A burst of faults contains faults that are consecutively injected into the array of memory blocks. After each fault in a burst is injected, one or more errors in one or more memory elements are detected and/or corrected. Information regarding the detection and/or the correction of an error is updated using registers that store counters. After injecting a burst of faults, the SEU controller waits for a predetermined amount of time. While waiting for a predetermined amount of time, the system monitors the system response to the burst of faults, such as monitoring the system for failures. After waiting, the SEU controller determines whether to inject another burst of faults. Bursts of faults are injected into the plurality of memory blocks until a system failure is detected or until the pattern scheme indicates to no longer inject bursts of faults into the memory.

Single event-upset controller wrapper that facilitates fault injection

A system includes a forwarding engine to schedule when replicas of a received multicast packet are forwarded towards one or more multicast recipients. The system also includes an egress interface device to replicate the multicast packet and forward the multicast packet replica towards the one or more multicast recipients when prompted by the forwarding engine based on the scheduling.

Distributed multicast packet replication with centralized quality of service

A method and network device for re-ordering segments of a segmented data stream. The method includes receiving at least two segments of a segmented data stream. A descriptor for each of the at least two segments is obtained, and the at least two segments are re-ordered to generate re-ordered segments, where the re-ordered segments are in an original order. A set of re-ordered segments are processed to obtain at least one data packet, where at least one descriptor is utilized in the processing of the set of re-ordered segments.

Re-ordering segments of a large number of segmented service flows

Methods and apparatus for reducing the average delay associated with sending a packet from one environment to another via a store and forward buffer are disclosed. According to one aspect of the present invention, a method for processing transmission units received over a first network connection includes receiving a first transmission unit on the first network connection, storing the first transmission unit in a buffer, and determining when contents of the buffer meet a plurality of criteria. The method also includes sending a backpressure over the first network connection when it is determined that the contents of the buffer meet the plurality of criteria. In one embodiment, determining when the contents of the buffer meet a plurality of criteria includes determining when the contents of the buffer are of an amount that exceeds a threshold and determining when the contents of the buffer include at least one full packet.

Reducing latency jitter in a store-and-forward buffer for mixed-priority traffic

A linecard architecture for high speed routing of data in a communications device. This architecture provides low latency routing based on packet priority: packet routing and processing occurs at line rate (wire speed) for most operations. A packet data stream is input to the inbound receiver, which uses a small packet FIFO to rapidly accumulate packet bytes. Once the header portion of the packet is received, the header alone is used to perform a high speed routing lookup and packet header modification. The queue manager then uses the class of service information in the packet header to enqueue the packet according to the required priority. Enqueued packets are buffered in a large memory space holding multiple packets prior to transmission across the device's switch fabric to the outbound linecard. On arrival at the outbound linecard, the packet is enqueued in the outbound transmitter portion of the linecard architecture. Another large, multi-packet memory structure, as employed in the inbound queue manager, provides buffering prior to transmission onto the network.

Architecture for high speed class of service enabled linecard

A crossbar switch is provided that can allocate output port bandwidth both among multiple classes of service and among input ports. In one implementation, there are two scheduling stages that may be implemented together. One scheduling stage can select traffic for output based on class of service whereas the other scheduling stage may perform a further selection based on destination output port. This allows greater flexibility in managing congestion and allocating limited available bandwidth.

Traffic management scheme for crossbar switch

A method to guarantee bandwidth for a terabit multiservice switch including receiving control cells indicating that a destination port of an asynchronous transfer mode (ATM) network is congested, and reducing incoming traffic to the congested port to a guaranteed bandwidth of traffic until the destination port is uncongested, is disclosed.

Guaranteed bandwidth mechanism for a terabit multiservice switch

A method and system for reordering data units that are to be written to, or read from, selected locations in a memory are described herein. The data units are reordered so that an order of accessing memory is optimal for speed of reading or writing memory, not necessarily an order in which data units were received or requested. Packets that are received at input interfaces are divided into cells, with cells being allocated to independent memory banks. Many such memory banks are kept busy concurrently, so cells (and thus the packets) are read into the memory as rapidly as possible. The system may include an input queue for receiving data units in a first sequence and a set of storage queues coupled to the input queue for receiving data units from the input queue. The data units may be written from the storage queues to the memory in an order other than the first sequence. The system may also include a disassembly element for generating data units from a packet and a reassembling element for reassembling a packet from the data units.

Method and apparatus for reordering packet data units in storage queues for reading and writing memory

In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.

Input/output system for multiprocessors

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Cupertino, CA, United States of America

Yie-Fong Dan