Intel Corporation

Yidnekachew S Mekonnen

Kemal Aygun

Mathew J Manusharow

Adel A Elsherbini

Aleksandar Aleksov

Feras Eid

Zhichao Zhang

Krishna Bharath

Henning Braunisch

Zhiguo Qian

Javier Soto

Sujit Sharan

Jianyong Xie

Sanka Ganesan

Mihir K Roy

Rajasekaran Swaminathan

Javier Soto Gonzalez

Suddhasattwa Nad

Jeff C Morriss

Meizi Jiao

Eduard Roytman

James A McCall

John Stephen Guzek

Ravindranath Vithal Mahajan

Saikumar Jayaraman

Wilfred Gomes

Ram S Viswanath

Digvijay Ashokkumar Raorane

Sriram Srinivasan

Richard J Dischler

Dae-Woo Kim

Gregorio R Murtagian

Chong J Zhao

Yu Zhang

Kevin Joseph Doran

Yu Amos Zhang

Christopher S Baldwin

Nevin Altunyurt

Robert J Friar

Nathan Fritz

Kemel Aygun

San K Chhay

Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins. In some examples, a second group of pins includes a first group of DQ pins separated by at least two VSS pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, the second group of pins, DQS pins are positioned between the first and third groups of DQ pins and the second and fourth groups of DQ pins.

Package pin pattern for device-to-device connection

Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Low loss and low cross talk transmission lines with stacked dielectric layers for forming stubs of different thickness or for forming a coaxial line

A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

Multiple die package using an embedded bridge connecting dies

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

Horizontal pitch translation using embedded bridge dies

An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.

Minimization of insertion loss variation in through-silicon vias (TSVs)

Passive semiconductor components and switches may be formed directly in, on, about, or across each of two or more semiconductor dies included in a stacked-die semiconductor package. At least some of the passive semiconductor components and/or switches may be formed in redistribution layers operably coupled to corresponding semiconductor dies included in the stacked-die semiconductor package. The switches may have multiple operating states and may be operably coupled to the passive semiconductor components such that one or more passive semiconductor components may be selectively included in one or more circuits or excluded from one or more circuits. The switches may be manually controlled or autonomously controlled using one or more control circuits. The one or more control circuits may receive one or more input signals containing host system information and/or data that is used to adjust or set the operating state of at least some of the switches.

Tunable passive semiconductor elements

Low loss and low cross talk transmission lines having l-shaped cross sections

Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.

EMIB copper layer for signal and power routing

Embodiments include packages substrates and a method of forming the package substrate. A package substrate includes a first dielectric comprising a first conductive layer, and a second dielectric comprising a second conductive layer and a third conductive layer. The second and third conductive layers are embedded in the second dielectric, where a top surface of the third conductive layer is above a top surface of the second conductive layer. The package substrate has a fourth conductive layer on the second dielectric. The first dielectric has a first dielectric thickness between the first and third conductive layers. The first dielectric also has a second dielectric thickness between the first and second conductive layers. The package substrate includes the second dielectric thickness that is greater than the first dielectric thickness. The second dielectric may have a z-height of a first bottom surface greater than a z-height of a second bottom surface.

Method to achieve variable dielectric thickness in packages for better electrical performance

Technology for simplified multimode signaling includes determining first and second self &#x3b1;-terms, cross coupling &#x3b1;-terms, and a delay skew term. For each communication link bundled in groups, the signals can be modulated as a superposition of the signals delayed and weighted based on the first and second self &#x3b1;-terms, the cross coupling &#x3b1;-terms and the delay skew term.

Simplified multimode signaling techniques

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

Package power delivery using plane and shaped vias

Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

Rlink&#x2014;die to die channel interconnect configurations to improve signaling

Packaged device including a transmission line associated with one of a conductive shield, vertical stubs, and vertically interdigitated stubs

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Chandler, AZ, United States of America

Yidnekachew S Mekonnen