Advanced Micro Devices Corporation

Spansion LLC.

Other

Fasl LLC

Globalfoundries Inc.

Advanced Micro Device, Inc.

Yider Wu

Mark T Ramsbey

Jean Y Yang

Yu Nan Sun

Hidehiko Shiraiwa

Jean Yee-Mei Yang

Angela Tai Hui

Kuo-Tung Chang

Unsoon Kim

Hiroyuki Ogawa

Chi K Chang

Bin Yu

Michael Allen Van Buskirk

Darlene G Hamilton

Narbeh Derhacobian

Ravi S Sunkavalli

Zhizheng Liu

Jiang Li

David Michael Rogers

Janet S Wang

Minh Van Ngo

Nian Niles Yang

Tuan Duc Pham

Haihong Wang

Hiroyuki Kinoshita

Tazrien Kamal

Rinji Sugino

Harpreet Kaur Sachar

Emmanuil Lingunis

Jeffrey Sinclair Glick

Emmanuel H Lingunis

Michael K Templeton

Jeffrey Allan Shields

Arvind Halliyal

John JianShi Wang

Mark S Chang

Dawn M Hopper

Nicholas H Tripsas

Yi He

Shibly S Ahmed

Krishnashree Achuthan

Kuo Tung Chang

Che-Hoo Ng

Edward Hsia

Kulachet Tanpairoj

Jusuke Ogura

Wiley Eugene Hill

Amy C Tu

Michael K Han

Mark E Ramsbey

Emmanuil Manos Lingunis

A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.

System and method for improving reliability in a semiconductor device

A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.

System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device

A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

Method for forming a semiconductor layer with improved gap filling properties

A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

System and method for improving mesa width in a semiconductor device

Method for forming a semiconducting layer with improved gap filling properties

The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the substrate and the STI structure. The recess formed within the first polysilicon layer is over the STI structure and extends through the first polysilicon layer to the STI structure. An oxide fill is provided within the recess and is etched back. ONO (oxide-nitride-oxide) layer conformally covers the oxide fill and the first polysilicon layer. The second polysilicon layer covers the ONO layer. The oxide fill within the recess provides a minimum spacing between the second polysilicon layer and the corner of the STI regions, thereby avoiding the creation of a weak spot and reducing the risk of gate breakdown, gate leakage, and improving device reliability.

Flash memory device and method of forming the same with improved gate breakdown and endurance

A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.

Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer

A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

Avoiding field oxide gouging in shallow trench isolation (STI) regions

A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.

Method and device for reducing interface area of a memory device

According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.

Memory structure having tunable interlayer dielectric and method for fabricating same

More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above the first metal layer. The ESDP device resides in the substrate below the first metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the ESDP component. Subsequent metal layers can be arranged between the first and second metal layers. The Ohmic value of the resistance component of the ESDP device can be set during fabrication by fixing a number of individual via components, arranged electrically in parallel, by fixing the cross sectional area of the via components, and/or by fixing the length of the via components.

Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance

A non-volatile memory device includes a substrate, an insulating layer, a fin, a number of dielectric layers and a control gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The dielectric layers are formed over the fin and the control gate is formed over the dielectric layers. The dielectric layers may include oxide-nitride-oxide layers that function as a charge storage structure for the memory device.

Non-volatile memory device

A non-volatile memory device includes a substrate, an insulating layer, a fin, a conductive structure and a control gate. The insulating layer may be formed on the substrate and the fin may be formed on the insulating layer. The conductive structure may be formed near a side of the fin and the control gate may be formed over the fin. The conductive structure may act as a floating gate electrode for the non-volatile memory device.

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Campbell, CA, United States of America

Yider Wu