Tencent Technology (shenzhen) Company Limited

Tencent Technology Company Limited

Yicong Zheng

Shengyu Zhang

Yuqin Chen

Changyu Hsieh

Hualiang Zhang

Mengyu Zhang

Guanglei Xi

Kaili Ma

Fuming Liu

Yu Zhou

Zhenxing Zhang

Wenlong Zhang

Yarui Zheng

Sainan Huai

Chuhong Yang

Maochun Dai

Qiaonian Yu

Lei Xie

This application discloses a clock synchronization system, including a quantum control processor (QCP) and N digital/analog mutual conversion devices, each digital/analog mutual conversion device including a frequency conversion module and a signal synchronization module that includes a D flip-flop (DFF). The QCP generates a global synchronization signal and reference clock signals; and transmits the global synchronization signal and a reference clock signal to the frequency conversion module and transmits the global synchronization signal to the signal synchronization module of each conversion device. The frequency conversion module performs frequency conversion processing on the reference clock signal to obtain a target clock signal, and generates a signal synchronization instruction according to the global synchronization signal; and transmits the signal synchronization instruction and the target clock signal to the signal synchronization module. The signal synchronization module performs, based on the global synchronization signal, signal synchronization on the target clock signal through the DFF.

Clock synchronization system, signal synchronization control method, and storage medium

This application discloses methods and devices for a quantum chip, a quantum processor and a quantum computer, and relates to the field of quantum technology. The quantum chip includes a bottom sheet and a top sheet; a qubit array disposed on the top sheet, the qubit array comprising a plurality of qubits distributed in an array structure of M rows by N columns, and M and N being both integers greater than 1; a reading cavity disposed on the bottom sheet, and the reading cavity being configured to acquire status information of a qubit in the qubit array; and the bottom sheet and the top sheet being electrically connected.

Quantum chip, quantum processor and quantum computer

This disclosure describes a quantum noise process analysis method, device, and storage medium, in the field of quantum processing technologies. The method may include performing quantum process tomography (QPT) on a quantum noise process of a target quantum system, to obtain dynamical maps of the quantum noise process, wherein the QPT involves at least one measurement of the target quantum. The method further includes extracting transfer tensor maps (TTMs) of the quantum noise process from the dynamical maps; and analyzing the quantum noise process according to the TTMs. The TTM is used for representing a dynamical evolution of the quantum noise process to reflect the law of evolution of the dynamical maps of the quantum noise process over time. As a result, richer and more comprehensive information about the quantum noise process can be obtained by analyzing the quantum noise process based on the TTM of the quantum noise process than by pure QPT, thereby achieving a more accurate and more comprehensive analysis of the quantum noise process.

Quantum noise process analysis method and apparatus, device, and storage medium

This application discloses a fault tolerant computation method and device for a quantum Clifford circuit with reduced resource requirement. The method includes decomposing a quantum Clifford circuit into s logic Clifford circuits and preparing auxiliary quantum states corresponding to the s logic Clifford circuits. For each logic Clifford circuit, the method further includes teleporting an input quantum state corresponding to the logic Clifford circuit to an auxiliary qubit, processing a quantum state obtained after the teleportation by the logic Clifford circuit to obtain a corresponding output quantum state; measuring a corresponding error symptom based on the input quantum state and the auxiliary quantum state; and performing error correction on the output quantum state according to the error symptom to obtain an error-corrected output quantum state.

Fault tolerant computation method and apparatus for quantum Clifford circuit, device, and chip

This disclosure discloses a fault tolerant and error correction decoding method and apparatus for a quantum circuit, and a chip. This disclosure relates to the field of artificial intelligence (AI) and quantum technologies. The method includes: obtaining actual error syndrome information of a quantum circuit by performing a noisy error syndrome measurement on the quantum circuit by using a quantum error correction (QEC) code; decoding the actual error syndrome information to obtain a logic error class and perfect error syndrome information that correspond to the actual error syndrome information; and determining error result information of the quantum circuit based on the logic error class and the perfect error syndrome information, the error result information being indicative of a data qubit in which an error occurs in the quantum circuit and a corresponding error class.

Fault tolerant and error correction decoding method and apparatus for quantum circuit, and chip

A quantum error correction (QEC) decoding system includes an error correction chip. The error correction chip is configured to: obtain error syndrome information of a quantum circuit; and decode the error syndrome information by running neural network decoders, to obtain error result information, a core operation of the neural network decoders being a multiply accumulate (MA) operation of unsigned fixed-point numbers obtained through numerical quantization. According to the present disclosure, for the system that uses the neural network decoders for QEC decoding, the core operation of the neural network decoders is the MA operation of unsigned fixed-point numbers obtained through numerical quantization, thereby minimizing the data volume and the calculation amount desirable by the neural network decoders, so as to better meet the requirement of real-time error correction.

Quantum error correction decoding system and method, fault-tolerant quantum error correction system, and chip

This application discloses a neural network-based QEC decoding method. The method includes: obtaining error syndrome information of a quantum circuit; performing block feature extraction on the error syndrome information by using a neural network decoder, to obtain feature information; and performing fusion decoding processing on the feature information by using the neural network decoder, to obtain error result information, the error result information being used for determining a data qubit in which an error occurs in the quantum circuit and a corresponding error type. In this application, a block feature extraction manner is used, a quantity of channels of feature information obtained by each feature extraction is reduced, and inputted data of next feature extraction is reduced, which reduces a quantity of feature extraction layers in a neural network decoder. Therefore, a decoding time used by the neural network decoder is reduced, thereby achieving real-time error correction.

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Guangdong, China

Yicong Zheng